Applied Materials Assigned Patent

Applied Materials, Inc., Santa Clara, CA, has been assigned a patent (10,541,246) developed by Purayath, Vinod R., Los Gatos, CA, for “3D flash memory cells which discourage cross-cell electrical tunneling .“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”3-D flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs which reduces the quantum probability of electron tunneling between vertically adjacent storage cells. The devices and methods further include a high work function nanocrystalline metal in the compound floating gate. A polysilicon buffer layer forms a portion of the compound floating gate. The polysilicon buffer layer allows the high work function nanocrystalline metal to be selectively deposited. The polysilicon buffer layer further protects the high work function nanocrystalline metal from oxidation with the gate oxide subsequently formed on the other side.”

The patent application was filed on April 30, 2018 (15/966,989).