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Technion Research and Development Foundation Assigned Two Patents

Retired page utilization for improved write capacity of SSD, memristor-based multithreading

Retired page utilization, ( RPU) for improved write capacity of SSD
Technion Research and Development Foundation Ltd., Haifa, Israel, has been assigned a patent (10,521,339) developed by Birk, Yitzhak, Hod Hasharon, Israel, and Berman, Amit, Nahariya, Israel, for a “
retired page utilization, (RPU) for improved write capacity of solid state drives.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells, searching for a selected retired group of memory cells that can store a representation of the data unit without being erased, and writing the representation of the data unit to the selected retired group of memory cells.

The patent application was filed on February 27, 2014 (14/191,471).

Memristor based multithreading
Technion Research and Development Foundation Ltd., Haifa, Israel, has been assigned a patent (10,521,237) developed by Kolodny, Avinoam, Haifa, Israel, Weiser, Uri, Tel Aviv, Israel, and Kvatinsky, Shahar, Ramat Gan, Israel, for a “
memristor based multithreading.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions, multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions, and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

The patent application was filed on March 19, 2014 (14/219,030).

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