R&D: Mitigating Write Disturbance in PCM Architectures
Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, don't cause disturbance errors in neighboring cells during PCM writes.
This is a Press Release edited by StorageNewsletter.com on January 14, 2020 at 2:19 pmIEEE Xplore has published, in 2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems (CASES) proceedings, an article written by Chao-Hsuan Huang, and Ishan G Thakkar, University of Kentucky, Department of Electrical and Computer Engineering, Lexington, KY, USA.
Abstract: “Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing ‘0s’ in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing ‘0s’ in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.“
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