Western Digital Technologies Assigned Eighteen Patents

Magnetic storage device with heat-assisted magnetic storage head and associated method of manufacture
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,468,071) developed by Tasaka, Kenji, Yokohama, Japan, Sano, Yuichiro, Sagamihara, Japan, Rismaniyazdi, Ehsan, Stipe, Barry, San Jose, CA, Okunaga, Nobuyuki, Odawara, Japan, Schreck, Erhard, Ruiz, Oscar, Dai, Qing, San Jose, CA, Canchi, Sripathi V., Sunnyvale, CA, Huang, Weidong, Palo Alto, CA, Hu, Yong, San Ramon, CA, and Kuroki, Kenji, Fujisawa, Japan, for a “magnetic storage device with heat-assisted magnetic storage head and associated method of manufacture.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein is a magnetic storage device that comprises a housing defining an interior cavity. The magnetic storage device also comprises at least one magnetic disk in the interior cavity of the housing. The magnetic storage device further comprises at least one read-write head in the interior cavity and configured to read data from and write data to the magnetic disk. The read-write head comprises a heat-assisted magnetic storage, (HAMR) head. The magnetic storage device additionally comprises a gas, comprising oxygen and helium, sealed in the interior cavity of the housing. A percent concentration of oxygen in the gas is greater than or equal to 3%. A pressure of the gas is between 10% and 70%, inclusive, of atmospheric pressure. A relative humidity within the interior cavity is less than 5%, inclusive. A percent concentration of helium in the gas is less than or equal to 90%.”

The patent application was filed on June 1, 2018 (15/996,092).

Slider with multiple-channel air-bearing surface
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,468,059) developed by Liu, Nan, San Jose, CA, for a “slider with multiple-channel air-bearing surface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed are sliders for data storage devices, and data storage devices incorporating such sliders. A slider comprises a leading edge and an air-bearing surface, (ABS). The ABS comprises a trailing end comprising a trailing pad, and a plurality of channels configured to direct gas in a direction from the leading edge toward the trailing end, wherein each of the plurality of channels is connected to the trailing end. The plurality of channels may include a center channel, an inner-diameter channel, and/or an outer-diameter channel. The disclosed sliders may be particularly advantageous for lower-pressure operating environments, such as sealed-helium disk drives.”

The patent application was filed on October 10, 2018 (16/156,626).

Magnetic write head with tapered return pole
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,468,058) developed by Bashir, Muhammad Asif, San Jose, CA, Van Der Heijden, Petrus Antonius, Cupertino, CA, and Matsumoto, Takuya, Sunnyvale, CA, for a “magnetic write head with a tapered return pole.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein are HAMR-enabled write heads for data storage devices, data storage devices comprising such HAMR-enabled write heads, and methods of fabricating such HAMR-enabled write heads. A HAMR-enabled write head comprises a leading side, a trailing side, an air-bearing surface (ABS), a main pole disposed between the leading side and the trailing side and extending to the ABS, a return pole comprising a tapered portion at the ABS, wherein the tapered portion is disposed between the main pole and the leading side and extends toward the main pole, and a waveguide disposed between the main pole and the return pole.”

The patent application was filed on June 28, 2018 (16/022,273).

Flexure and actuator for magnetic recording
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,468,057) developed by Naniwa, Irizo, Fujisawa, Japan, Tsuchiya, Tatsumi, Hachioji, Japan, and Nakamura, Shigeo, Odawara, Japan, for “flexure and actuator system for magnetic recording device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A magnetic storage device comprising a magnetic disk and a carriage arm rotatably movable relative to the magnetic disk. A suspension assembly of the magnetic storage device is coupled to the carriage arm and comprising a flexure. The magnetic storage device additionally comprises a slider comprising a read-write head. The flexure comprises a fixed portion co-movably fixed relative to the carriage arm and a hinge portion to which the slider is co-movably fixed. The hinge portion is swayable relative to the fixed portion. An actuator system of the magnetic storage device is coupled to the fixed portion of the flexure and the hinge portion of the flexure. The actuator system is operable to sway the hinge portion relative to the fixed portion. The magnetic storage device includes a repolarization enhancing feature adjacent the actuator system.”

The patent application was filed on February 28, 2018 (15/908,338).

Write head having monolithic side sheild and leading shield
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,468,054) developed by Shin, Kyusik, Pleasanton, CA, Chen, Yingjian, Fremont, CA, Leung, Jennifer, and Park, Munhyoun, San Jose, CA, for a “write head having a monolithic side sheild and leading shield.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to data storage devices, and more specifically, to a magnetic media drive employing a write head. The write head comprises a main pole and a monolithic side shield. A first leading shield is disposed below the side shield, and a second leading shield is disposed between the first leading shield and the side shield. The first leading shield has a greater throat height than a throat height of the second leading shield. A side shield throat height extending from the main pole to the side shield is shorter than the first leading shield throat height extending from the main pole to the first leading shield. The varying throat heights between the main pole, the side shield, and the first leading shield allow for enhanced cross-track recording density and reduce flux leakage from the main pole.”

The patent application was filed on August 22, 2018 (16/109,489).

High availability state machine and recovery
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,467,100) developed by Steffko, Ladislav, San Ramon, CA, and Karamcheti, Vijay, Palo Alto, CA, for a “high availability state machine and recovery.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.”

The patent application was filed on August 15, 2016 (15/236,818).

Conditional journal for storage class memory devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,467,074) developed by Gunnam, Kiran Kumar, Milpitas, CA, and Dubeyko, Viacheslav Anatolyevich, San Jose, CA, for a “conditional journal for storage class memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.”

The patent application was filed on December 30, 2016 (15/395,144).

Maximizing frequency while checking data integrity on physical interface bus
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,466,920) developed by Tzafrir, Yonatan, Petah Tikva, Israel, Zehavi, Mordekhay, Raanana, Israel, and Asfur, Mahmud, Bat-Yam, Israel, for a “method for maximizing frequency while checking data integrity on a physical interface bus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.”

The patent application was filed on August 17, 2017 (15/679,468).

Using logical based addressing for latency reduction
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,466,911) developed by Gerhart, Darin Edward, Oronoco, MN, Ortmeier, Nicholas Edward, Rochester, MN, and Erickson, Mark David, Mantorville, MN, for a “method using logical based addressing for latency reduction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command, populating at least one metadata frame with data based on logical block address latency information, initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.”

The patent application was filed on December 18, 2017 (15/845,005).

Accessing non-volatile memory express controller memory manager
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,466,906) developed by Benisty, Shay, Beer Sheva, Israel, for “accessing non-volatile memory express controller memory manager.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.”

The patent application was filed on December 19, 2017 (15/846,787).

Elimination of crosstalk effects in non-volatile storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,461,804) developed by Cohen, Moshe, Modi’in, Israel, and Ben-Rubi, Refael, Rosh Haayin, Israel, for “elimination of crosstalk effects in non-volatile storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for elimination of crosstalk effects in a non-volatile storage is disclosed, having steps of identifying at least one line connected to the non-volatile storage that causes crosstalk effects to another line connected to the non-volatile storage, sending a command to the non-volatile storage to replace the at least one line causing crosstalk effects, selecting at least one line to replace the at least one line causing crosstalk effects with a spare line and replacing the at least one line causing crosstalk effects with the spare line.”

The patent application was filed on January 25, 2018 (15/879,680).

Non-volatile memory and method for power efficient read or verify using lockout control
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,460,814) developed by Dak, Piyush, San Jose, CA, Dunga, Mohan Vamsi, Santa Clara, CA, and Shukla, Pitamber, Milpitas, CA, for “non-volatile memory and method for power efficient read or verify using lockout control.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.”

The patent application was filed on December 12, 2017 (15/838,863).

Multi-level phase change device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,460,801) developed by Lille, Jeffrey, and Franca-Neto, Luiz M., Sunnyvale, CA, for a “multi-level phase change device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.”

The patent application was filed on June 25, 2018 (16/017,806).

Slider and suspension arm interconnection for magnetic storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,460,754) developed by Matsumoto, Yuhsuke, Fujisawa, Japan, Murata, Kenichi, Ebina, Japan, Tokaew, Adisak, Muang, Thailand, Druist, David, Gee, Glenn, San Jose, CA, Moravec, Mark, Lamlukka, Thailand, Ranes, Michael, Looc Calamba, Philippines, and Dilla, Peter Paolo, Santa Rosa, Philippines, for “slider and suspension arm interconnection for magnetic storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein is a magnetic storage device that comprises a suspension arm co-movably fixed to a carriage arm. The suspension arm comprises a slider attachment side and at least one first electrical contact pad on the slider attachment side. The suspension arm also comprises a slider co-movably fixed to the suspension arm. The slider comprises a suspension attachment side, a non-head side facing the suspension arm and intersecting the suspension attachment side at a first slider edge of the slider, a head side facing away from the suspension arm, and at least one electrical contact component on the suspension attachment side up to the first slider edge. At least one solder weldment is directly coupled to the at least one first electrical contact pad and the at least one electrical contact component. Additionally, a read-write head is coupled to the head side of the slider.”

The patent application was filed on February 5, 2018 (15/888,449).

Spin-torque oscillator with multilayer seed layer
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,460,752) developed by Freitag, James Mac, Sunnyvale, CA, Gao, Zheng, Hashimoto, Masahiko, and Oh, Sangmun, San Jose, CA, for a “spin-torque oscillator with multilayer seed layer between the write pole and the free layer in a magnetic recording write head.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A magnetic recording write head and system has a spin-torque oscillator (STO) located between the write head’s write pole and trailing shield. The STO’s ferromagnetic free layer is located near the write pole with a multilayer seed layer between the write pole and the free layer. The STO’s nonmagnetic spacer layer is between the free layer and the STO’s ferromagnetic polarizer. The polarizer may be the trailing shield of the write head or a separate polarizer layer. The STO electrical circuitry causes electron flow from the write pole to the trailing shield. The multilayer seed layer removes the spin polarization of electrons from the write pole, which enables electrons reflected from the polarizer layer to become spin polarized, which creates the spin transfer torque on the magnetization of the free layer. The multilayer seed layer includes Mn or a Mn-alloy layer between one or more metal or metal alloy films.”

The patent application was filed on May 10, 2018 (15/976,750).

Stripe height lapping control structures for multiple sensor array
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,460,751) developed by Rudy, Steven C., Carmel Valley, CA, Beaudry, Christopher L., San Jose, CA, and Li, Shaoping, San Ramon, CA, for a “stripe height lapping control structures for a multiple sensor array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and system provide a storage device. A plurality of read sensor stacks for each reader of the storage device are provided. The read sensor stacks are distributed along a down track direction and offset in a cross-track direction. A plurality of electronic lapping guides (ELGs) are provided for the read sensor stacks. The read sensor stacks are lapped. Lapping is terminated based on signal(s) from the ELG(s).”

The patent application was filed on May 24, 2018 (15/988,122).

Replicating data across data storage devices of logical volume
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,891) developed by Neumann, Charles A., Lake Forest, CA, for a “replicating data across data storage devices of a logical volume.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for replicating data across data storage devices of a logical volume. A data storage system may create a logical volume by grouping the multiple data storage devices together. The data storage devices may be external standalone data storage devices. The data storage system may also replicate data across the logical volume.”

The patent application was filed on September 30, 2015 (14/870,943).

Managing flash memory read operations
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,844) developed by Benisty, Shay, Beer Sheva, Isael, Navon, Ariel, Revava, Isael, and Marcu, Alon, Tel-Mond, Isael, for “managing flash memory read operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to a storage device and method of managing flash memory read operations of a storage device. In one embodiment, a method of retrieving information stored in a storage device comprises determining a timing of a next host read command for a flash memory die. If there is a storage device initiated read request for the flash memory die is determined. In response to an identification of the storage device initiated read request, a random cache read operation is initiated with the storage device initiated read request bound with the next host read command.”

The patent application was filed on December 21, 2017 (15/851,706).