Western Digital Technologies Assigned Fifteen Patents

Data reliability information in a non-volatile memory device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,793) developed by Bandic, Zvonimir Z., San Jose, CA, Gunnam, Kiran Kumar, Milpitas, CA, and Song, Seung-Hwan, San Jose, CA, for a “data reliability information in a non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.”

The patent application was filed on March 17, 2016 (15/073,409).

Error detection for training non-volatile memories
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,785) developed by Dusija, Gautam Ashok, Burlingame, CA, Ramachandra, Venkatesh Prasa, and Kochar, Mrinal, San Jose, CA, for an “error detection for training non-volatile memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory, (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check, (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.”

The patent application was filed on September 27, 2017 (15/717,572).

Non-volatile storage system with integrated compute engine
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,644) developed by Mehra, Pankaj, and Mohan, Vidyabhushan, San Jose, CA, for a “non-volatile storage system with integrated compute engine and optimized use of local fast memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system, (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to, or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.”

The patent application was filed on October 6, 2017 (15/726,903).

Data storage device calibrating preamp clock using system clock
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,459,479) developed by Poss, Joey M., Rochester, MN, for a “data storage device calibrating preamp clock using system clock.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk, and preamp circuitry coupled to the head, wherein the preamp circuitry comprises a preamp clock and a clock counter configured to count cycles of the preamp clock. A start command over is transmitted from system circuitry over a serial interface to the preamp circuitry to begin counting a number of cycles of the preamp clock. The system circuitry receives a preamp command over the serial interface from the preamp circuitry, wherein the preamp command is based on the clock counter in the preamp circuitry. The system circuitry generates a frequency adjustment command based on the preamp command, and transmits the frequency adjustment command over the serial interface to the preamp circuitry in order to adjust a frequency of the preamp clock.”

The patent application was filed on March 31, 2018 (15/942,481).

Run-time flash die failure detection enhancement
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,453,548) developed by Chu, Sanghoon, San Jose, CA, Jinn, Scott, Diamond Bar, CA, and Pavlenko, Yuriy, Lake Forest, CA, for a “run-time flash die failure detection enhancement.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a ‘pass’ but a plane pass/fail bit indicates a ‘fail’ then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing.”

The patent application was filed on May 19, 2017 (15/600,673).

Wear leveling in non-volatile memories
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,560) developed by Gunnam, Kiran Kumar, Milpitas, CA, for a “wear leveling in non-volatile memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for wear leveling in non-volatile memories, (NVMs) are disclosed. One such system includes a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses, (PBAs) and logical block addresses, (LBAs) of an NVM, an access network configured to translate a LBA to a PBA based on the cumulative control state, and a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state. One such method involves determining a cumulative control state indicative of a state of random mappings between physical block addresses, (PBAs) and logical block addresses, (LBAs) of an NVM, translating a LBA to a PBA based on the cumulative control state, and swapping PBAs assigned to preselected LBAs based on a control state.”

The patent application was filed on June 19, 2017 (15/627,091).

Address range mapping for storage devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,558) developed by Genshaft, Igor, Bat Yam, Israel, and Frid, Marina, Jerusalem, Israel, for an “address range mapping for storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, methods, and computer program products are disclosed for address range mapping for memory devices. A system includes a set of non-volatile memory elements accessible using a set of physical addresses and a controller for the set of non-volatile memory elements. A controller is configured to maintain a hierarchical data structure for mapping logical addresses to a set of physical addresses. A hierarchical data structure comprises a plurality of levels with hashed mappings of ranges of logical addresses at range sizes selected based on a relative position of an associated level within the plurality of levels. A controller is configured to receive an I/O request for data of at least one logical address. A controller is configured to satisfy an I/O request using a hashed mapping having a largest available range size to map at least one logical address of the I/O request to one or more physical addresses.”

The patent application was filed on October 5, 2018 (16/153,561).

Direct write and mapping of data in non-volatile memory having multiple sub-drives
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,537) developed by Gorobets, Sergey Anatolievich, and Parker, Liam Michael, Edinburgh, Great Britain, for “system and method of direct write and mapping of data in a non-volatile memory having multiple sub-drives.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.”

The patent application was filed on April 16, 2018 (15/954,198).

Dynamic management of garbage collection and overprovisioning for host stream storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,536) developed by Parker, Liam Michael, Gorobets, Sergey Anatolievich, Edinburgh, Great Britain, and Acosta, Marc, Laguna Beach, CA, for “dynamic management of garbage collection and overprovisioning for host stream storage.“

The patent application was filed on October 13, 2017 (15/783,739).

Access network for address mapping in non-volatile memories
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,533) developed by Gunnam, Kiran Kumar, Milpitas, CA, for an “access network for address mapping in non-volatile memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for determining a physical block address, (PBA) of a non-volatile memory, (NVM) to enable a data access of a corresponding logical block address, LBA) are described. One such method includes generating a first physical block address, (PBA) candidate from a LBA using a first function, generating a second physical block address, PBA) candidate from the LBA using a second function, and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.”

The patent application was filed on March 3, 2017 (15/449,612).

Managing failure of SSD in caching storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,473) developed by Kazemi, Saied, Mountain View, CA, and Choudhuri, Siddharth, Irvine, CA, for “methods for managing failure of a solid state device in a caching storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques for managing caching use of a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for managing caching use of a solid state device. Management of the caching use may include receiving, at a host device, notification of failure of a solid state device. In response to the notification a cache mode may be set to uncached. In uncached mode input/output, (I/O) requests may be directed to uncached storage, (e.g., disk).”

The patent application was filed on December 21, 2015 (14/976,518).

Non-volatile memory with dynamic write abort detection and recovery
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,471) developed by Shen, Zhenlei, Milpitas, CA, Yang, Nian Niles, Mountain View, CA, and Cheng, Chao-Han, San Jose, CA, for “non-volatile memory with dynamic write abort detection and recovery.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.”

The patent application was filed on October 11, 2017 (15/730,454).

Managing non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,452,468) developed by Chu, Sanghoon, San Jose, CA, Jinn, Scott, Diamond Bar, CA, Pavlenko, Yuriy, Mission Viejo, CA, and Song, Kum-Jung, Santa Clara, CA, for “method and system for managing non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.”

The patent application was filed on December 30, 2016 (15/396,405).

Secure stream buffer on network attached storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,447,667) developed by Jenkins, Dean M., La Canada-Flintridge, CA, and Ryan, Robert P., Mission Viejo, CA, for a “secure stream buffer on network attached storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A network attached storage device coupled to a local network and including a network interface configured to receive digital content from a remote content provider outside the local network. The network attached storage device includes storage having a first region accessible by a user of the local network and a secure region. The network attached storage device includes a processor coupled to the storage, the processor configured to control access to the secure region of the storage based on instructions received from a remote content provider.”

The patent application was filed on April 16, 2018 (15/954,359).

Spin transfer torque device with oxide layer beneath seed layer
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,446,175) developed by Freitag, James Mac, Sunnyvale, CA, Okamura, Susumu, Hashimoto, Masahiko, and Gao, Zheng, San Jose, CA, for a “spin transfer torque device with oxide layer beneath the seed layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A spin transfer torque, (STT) device is formed on an electrically conductive substrate and includes a ferromagnetic free layer near the substrate, a ferromagnetic polarizing layer and a nonmagnetic spacer layer between the free layer and the polarizing layer. A multilayer structure is located between the substrate and the free layer. The multilayer structure includes a metal or metal alloy seed layer for the free layer and an intermediate oxide layer below and in contact with the seed layer. The intermediate oxide layer reflects spin current from the free layer and thus reduces undesirable damping of the oscillation of the free layer’s magnetization by the seed layer.”

The patent application was filed on May 16, 2017 (15/596,198).