Macronix Assigned Seven Patents

Three-dimensional non-volatile memory and manufacturing
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,424,593) developed by Lin, I-Ting, Hsinchu, Taiwan, Chiu, Yuan-Chieh, Hsinchu County, Taiwan, and, Lee, Hong-Ji, Taoyuan, Taiwan, for “three-dimensional non-volatile memory and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.”

The patent application was filed on January 9, 2018 (15/866,132).

Program scheme in 3D NAND flash memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,418,108) developed by Lin, Lee-Yin, Taipei, Taiwan, for a “program scheme in 3D NAND flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.”

The patent application was filed on March 20, 2018 (15/926,217).

Physical unclonable function using divided threshold distributions in non-volatile memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,404,478) developed by Hung, Chun-Hsiung, Hsinchu, Taiwan, Chang, Kuen-Long, Taipei, Taiwan, Chen, Ken-Hui, Hsinchu, Taiwan, and Huang, Shih-Chang, Penghu, Taiwan, for a “physical unclonable function using divided threshold distributions in non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array, utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks, and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.”

The patent application was filed on May 22, 2017 (15/601,515).

Discrete charge trapping elements for 3D NAND architecture
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,403,637) developed by Lue, Hang-Ting, Hsinchu, Taiwan, for a “discrete charge trapping elements for 3D NAND architecture.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.”

The patent application was filed on January 20, 2017 (15/410,965).

Capacitor with 3D NAND memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,388,720) developed by Lue, Hang-Ting, and Yeh, Teng-Hao, Hsinchu, Taiwan, for a “capacitor with 3D NAND memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.”

The patent application was filed on September 28, 2016 (15/279,203).

Te-free AsSeGe chalcogenides for selector devices and memory devices
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,374,009) developed by Cheng, Huai-Yu, White Plains, NY, Lung, Hsiang-Lan, Ardsley, NY, and Kuo, I-Ting, Taoyuan, Taiwan, for “Te-free AsSeGe chalcogenides for selector devices and memory devices using same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes, comprising a tellurium free, low germanium composition of arsenic As, selenium Se and germanium Ge. The switching device is used in 3D cross-point memory.”

The patent application was filed on July 17, 2018 (16/038,072).

Erase-verify method for three-dimensional memories and memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,340,017) developed by Ku, Shaw-Hung, Hsinchu, Taiwan, Huang, Yu-Hung, Tainan, Taiwan, Cheng, Cheng-Hsien, Yunlin County, Taiwan, Lee, Chih-Wei, New Taipei, Taiwan, Suzuki, Atsuhiro, Hsinchu, Taiwan, and Tsai, Wen-Jer, Hualien, Taiwan, for an “erase-verify method for three-dimensional memories and memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An erase-verify method for a three-dimensional, (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.”

The patent application was filed on November 6, 2017 (15/803,986).