SanDisk/WD Assigned Twelve Patents

Data storage device for device accessory
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,394,296) developed by Kashyap, Manohar Prasad, Hakoun, Eyal Felix, and Shain, Vadim, Milpitas, CA, for a “data storage device for a device accessory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus includes a first interface of an accessory of a wireless device. The first interface is configured to communicate with the wireless device using a wired communication technique. The apparatus includes a second interface of the accessory. The second interface is configured to communicate with the wireless device using a wireless communication technique. The apparatus also includes a data storage device of the accessory. The apparatus further includes a controller of the accessory. The controller is coupled to the first interface, to the second interface, and to the data storage device. The controller is configured to activate the first interface in response to a message received via the second interface.”

The patent application was filed on January 25, 2018 (15/879,751).

Synchronizing storage state information
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,382,540) developed by Van Assche, Bart, Salt Lake City, UT, Wipfel, Robert, Draper, UT, and Christie, Mike, Salt Lake City, UT, for a “synchronizing storage state information.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques are disclosed relating to synchronizing state information across nodes in a cluster. In one embodiment, a first cluster node receives a request to update state information for a logical volume of the cluster. The first cluster node acquires a lock from a distributed lock manager of the cluster, the lock controlling modification of the state information. In response to acquiring the lock, the first cluster node updates the state information across cluster nodes of the cluster. In one embodiment, first cluster node updates the state information in some, but not all, of the cluster nodes. In some embodiments, the first cluster node updates the state information across only cluster nodes associated with the logical volume.”

The patent application was filed on August 1, 2014 (14/449,834).

Three-dimensional phase change memory array
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,381,559) developed by Zhou, Fei, San Jose, CA, Makala, Raghuveer S., Campbell, CA, Petti, Christopher J., Mountain View, CA, Sharangpani, Rahul, Fremont, CA, Rajashekhar, Adarsh, San Jose, CA, and Yang, Seung-Yeul, Pleasanton, CA, for a “three-dimensional phase change memory array including discrete middle electrodes and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.”

The patent application was filed on June 7, 2018 (16/002,169).

Spin orbit torque magnetoresistive random access memory
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,381,551) developed by Lille, Jeffrey, Sunnyvale, CA, for “spin orbit torque magnetoresistive random access memory containing shielding element and method of making thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A Magnetoresistive Random Access Memory, (MRAM) assembly includes a first ferromagnetic shielding component, a second ferromagnetic shielding component, a plurality of MRAM cells located between the first and second ferromagnetic shielding components, a plurality of bit lines located between the first and second ferromagnetic shielding components, each bit line coupled to at least one of the plurality of MRAM cells, a plurality of word lines located between the first and second ferromagnetic shielding components, each word line coupled to at least one of the plurality of MRAM cells, a ferromagnetic yoke electrically connecting the first and second ferromagnetic shielding components, and located in an area of the assembly substantially free of the MRAM cells, bit lines, and word lines, and an insulator surrounding the magnetic yoke.”

The patent application was filed on June 29, 2018 (16/024,521).

Three-dimensional memory device containing conformal wrap around phase change material
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,381,411) developed by Lille, Jeffrey S., Sunnyvale, CA, for “three-dimensional memory device containing conformal wrap around phase change material and method of manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory cell includes a first electrode which extends horizontally over a substrate, a layer stack containing a phase change memory material layer and a threshold switch material layer which wrap around the first electrode, and a second electrode which contains a first vertical portion and a second vertical portion which extend vertically over the substrate and are located on first and second lateral sides of the layer stack.”

The patent application was filed on December 15, 2017 (15/844,005).

Three-dimensional phase change memory array including discrete middle electrodes
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,381,409) developed by Zhou, Fei, San Jose, CA, Makala, Raghuveer S., Campbell, CA, Petti, Christopher J., Mountain View, CA, Sharangpani, Rahul, Fremont, CA, Rajashekhar, Adarsh, San Jose, CA, and Yang, Seung-Yeul, Pleasanton, CA, for “three-dimensional phase change memory array including discrete middle electrodes and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.”

The patent application was filed on June 7, 2018 (16/002,243).

Three-dimensional flat NAND memory device including concave word lines
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,381,376) developed by Nishikawa, Masatoshi, Hu, Xiaolong, Yokkaichi, Japan, and Zhang, Yanli, San Jose, CA, for “three-dimensional flat NAND memory device including concave word lines and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by vertically undulating trenches. The vertically undulating trenches have a greater lateral extent at levels of the electrically conductive strips than at levels of the insulating strips. An interlaced two-dimensional array of memory stack assemblies and dielectric pillar structures are located in the vertically undulating trenches. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory films including a respective pair of convex outer sidewalls that contact, or are spaced by a uniform distance from, concave sidewalls of the electrically conductive strips. Local electrical field at laterally protruding tips of the vertical semiconductor channels are enhanced due to the geometric effect provided by the concave sidewalls of the electrically conductive strips to facilitate faster program and erase operations.”

The patent application was filed on June 7, 2018 (16/002,294).

Storage system and method for improved command flow
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,379,781) developed by Yarovoy, Boris, Maalot-Tarshiha, Israel, for “storage system and method for improved command flow.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system and method for improved command flow are provided. In one embodiment, a storage system receives a request from a host for an indication of which command(s) stored in the storage system are ready for execution, in response to the request, provides the host with the indication of which command(s) stored in the storage system are ready for execution, receives an instruction from the host to execute a command that is ready for execution, and in response to the instruction from the host to execute the command, performs both of the following: executes the command and provides the host with an updated indication of which command(s) stored in the storage system are ready for execution, wherein the storage system provides the host with the updated indication without receiving a separate request from the host for the updated indication. Other embodiments are provided.”

The patent application was filed on April 20, 2016 (15/134,104).

Multi-state phase change memory device with vertical cross-point structure
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,374,014) developed by Nardi, Federico, San Jose, CA , Petti, Christopher J, Mountain View, CA, and Hemink, Gerrit Jan, San Ramon, CA, for a “multi-state phase change memory device with vertical cross-point structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory uses phase change memory, (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.”

The patent application was filed on January 12, 2018 (15/869,592).

Non-volatile storage systems with go to sleep adaption
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,365,841) developed by Elhamias, Reuven, Kfar Vradim, Israel, and Fishler, Ram, M.P. Misgav, Israel, for a “non-volatile storage systems with go to sleep adaption.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.”

The patent application was filed on July 13, 2015 (14/798,199).

Three-dimensional memory device with amorphous barrier layer
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,355,139) developed by Sharangpani, Rahul, Fremont, CA, Makala, Raghuveer S., Campbell, CA, Shukla, Keerti, Saratoga, CA, Zhou, Fei, Milpitas, CA, and Peri, Somesh, San Jose, CA, for a “three-dimensional memory device with amorphous barrier layer and method of making thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.”

The patent application was filed on October 12, 2016 (15/291,640).

Three-dimensional NAND memory device with common bit line for multiple NAND strings
SanDisk Technologies LLC, Plano, TX, has been assigned a patent (10,355,015) developed by Zhang, Yanli, San Jose, CA, Kai, James, Santa Clara, CA, and Alsmeier, Johann, San Jose, CA, for a “three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.”

The patent application was filed on April 9, 2018 (15/948,737).