Lite-On Assigned Two Patents

Erased block reverification method for solid state storage device
Lite-On Electronics, (Guangzhou), Guangzhou, China, and Lite-On Technology Corp., Taipei, Taiwan, has been assigned a patent (10,403,379) developed by Kuo, Chun-Wei, Huang, Ding-Chiuan, and Zeng, Shih-Jia, Taipei, Taiwan, for an “erased block reverification method for solid state storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An erased block reverification method for a solid state storage device is provided. Firstly, an erase command corresponding to a selected block is issued to an array control circuit. When an erase pass message is received, a judging step is performed to judge whether a setting condition of the selected block is satisfied. If the setting condition of the selected block is satisfied, the selected block is recorded as a good block. If the setting condition of the selected block is not satisfied, a selected block reverification process is performed. During the selected block reverification process, a data of the selected block is read and the selected block is recorded as the good block or a defective block according to a number of memory cells of the selected block in a non-erase state.”

The patent application was filed on July 9, 2018 (16/029,784).

SSD and program loading
Lite-On Electronics, (Guangzhou), Guangzhou, China, and Lite-On Technology Corp., Taipei, Taiwan, has been assigned a patent (10,379,875) developed by Chen, Ping-Jie, Chang, Sheng-Yu, and, Weng, Chien-Chih, Taipei, Taiwan, for “solid state storage device and program loading method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a first storage zone and a second storage zone. A boot code loader is stored in the first storage zone. The non-volatile memory includes a memory cell array. The memory cell array includes a third storage zone and a fourth storage zone. A specified program is stored in the third storage zone. The third storage zone contains a first block. A first page of the first block is divided into a first portion and a second portion. A first binary code of the specified program is repeatedly stored in plural bytes of the first portion of the first page. The one’s complement of the first binary code is repeatedly stored in plural bytes of the second portion of the first page.”

The patent application was filed on January 16, 2018 (15/872,004).