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R&D: Pre-shipment Data-Retention/Read-Disturb Lifetime Prediction & Aftermarket Cell Error Detection and Correction for 3D-TLC NAND Flash Memory

By Neural Network

IEEE Xplore has published, in 2019 Symposium on VLSI Technology proceedings, an article written by Masaki Abe, Toshiki Nakamura, and Ken Takeuchi, Chuo University, 1-13-27 Kasuga, Bunkyo-ku, Tokyo, 112-8551, Japan.

Abstract:This paper proposes two neural network (NN) techniques for 3D-TLC (Triple-Level Cell) NAND flash memory. 1) Predict data-retention/read-disturb lifetime for chip sorting during preshipment test. 2) Detect and correct errors in aftermarket. First, in pre-shipment test, Neural Network-based Lifetime Prediction (NNLP) predicts ECC decoding fail rate (EDFR) and estimates data-retention/read-disturb lifetime. Based on predicted lifetime, NNLP sorts NAND flash. Second, in aftermarket, Neural Network-based Error Detection (NNED) detects and corrects errors. NNED decreases bit-error rate (BER) by 81.4%.

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