Shenzhen Epostar Electronics Assigned Two Patents

Data moving and storage controller
Shenzhen Epostar Electronics Ltd. Co, Shenzhen, China, has been assigned a patent (10,339,046) developed by Hsieh, Hung-Chih, and Hsiao, Yu-Hua, Hsinchu County, Taiwan, for “data moving method and storage controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data moving method and a storage controller are provided. The method includes: when obtained valid data is sequential data, transmitting a first read command to read a first data and a second data from a first plane and a second plane of a first die, transmitting a second read command to read a third data and a fourth data from a first plane and a second plane of a second die, and transmitting the first data, the third data, the second data and the fourth data to a buffer memory in an order, and transmitting a first programming command to program the first data and the second data to a first plane and a second plane of a third die, and transmitting a second programming command to program the third data and the fourth data to a first plane and a second plane of a fourth die.”

The patent application was filed on May 9, 2018 (15/974,707).

Valid data management and storage controller
Shenzhen Epostar Electronics Ltd. Co, Shenzhen, China, has been assigned a patent (10,339,045) developed by Chu, Hsiu-Hsien, Hsinchu, Taiwan, Hsieh, Hung-Chih, and Hsiao, Yu-Hua, Hsinchu County, Taiwan, for “valid data management method and storage controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A valid data management method and a storage controller are provided. The method includes creating a valid data mark table and a valid logical addresses table corresponding to a target physical unit according to a logical-to-physical table and a target physical-to-logical table corresponding to the target physical unit, wherein the valid data mark table records a plurality of mark values respectively corresponding to a plurality of target logical addresses, the mark values respectively indicate whether the corresponding logical addresses is valid or invalid, and the valid logical addresses table only records one or more valid target logical addresses according to an order of one or more first bit values in the valid data mark table, and identifying one or more valid data of the target physical unit according to the logical-to-physical table, the valid data mark table and the valid logical addresses table corresponding to the target physical unit.”

The patent application was filed on April 25, 2018 (15/961,906).