IQ-Analog Assigned Patent
NAND logic gate with data-independent delay
By Francis Pelletier | July 16, 2019 at 1:51 pmIQ-Analog Corporation, San Diego, CA, has been assigned a patent (10,333,524) developed by Mattia, Oscar Elisio, San Diego, CA, for a “NAND logic gate with data-independent delay.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.”
The patent application was filed on March 7, 2019 (16/295,138).