R&D: Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory

IEEE Xplore has published, in 2018 Ninth International Green and Sustainable Computing Conference (IGSC) proceedings, an article written by Seyed Mohammad Seyedzadeh, Computer Science, University of Pittsburgh, Alex K. Jones, Electrical and Computer Engineering, University of Pittsburgh, and Rami Melhem, Computer Science, University of Pittsburgh.

Abstract: ”Phase change memory (PCM) is a popular emerging technology for next generation systems. PCM provides advantages compared to conventional memories such as DRAM and Flash including reduced static energy, density advantages over DRAM, and performance and endurance advantages over Flash. Some limitations of PCM, including high dynamic energy and limited endurance can be improved through intelligent encoding. Unfortunately, the additional density benefits achieved through technology scaling increases the proximity between cells and for technologies below 22nm, which can lead to inadvertent writing, referred to as write disturbance, both within the active wordline (i.e., row) and across neighboring wordlines (rows). Write disturbance results in significant system inefficiency to check and rewrite disturbed cells. In this paper, we develop a multi-tiered compression technique that compresses by a small amount (e.g., 40- or 56-bits of a 512-bit block) for >94% of cachelines stored into memory (e.g., during eviction) without disturbing data locality vital for optimizing PCM writes. Using this recovered space, we design a one-to-one mapping that probabilistically detects the cells likely to disturb neighboring cells. Using encoding, correction pointers, and a hybrid approach, we can reduce the instances of write disturbance. Due to using reclaimed bits for encoding, the proposed technique requires only five (5) additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Our experimental tests shows that the proposed technique successfully reduces the number of disturbed cells, which can be directly translated to the number of extra write and read operations, required for disturbance error mitigation. Specifically, our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the leading approach with minimal (circa 1%) increases to embodied energy.”