Seagate Assigned Fourteen Patents

Intelligent backup capacitor management
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,283,173) developed by Narayanan, Sathish, Tamilnadu, India, Vithalkar, Vinayak, Karnataka, India, Pradeep, Eric Pius, Tamilnadu, India, for an “intelligent backup capacitor management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods and apparatuses for intelligently managing backup capacitors in a storage device. The power consumption of the device is monitored in order to determine a current backup energy requirement comprising an amount of energy needed to power the device for data-backup and power-down operations in the event of an interruption of main power to the device. Based on the current backup energy requirement, one or more of a plurality of backup capacitors of the device are turned on or off, wherein the plurality of backup capacitors are configured such that those of the plurality of backup capacitors remaining in the on state provide backup energy to the device during the interruption of main power.”

The patent application was filed on April 19, 2017 (15/491,615).

Near-field transducer with dielectric slit at internal surfaces
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,283,152) developed by Peng, Chubing, Eden Prairie, MN, Wessel, James Gary, Savage, MN, and Lee, Lien, Maple Grove, MN, for a “near-field transducer with a dielectric slit at internal surfaces for controlling feedback to a light source.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A recording head includes a waveguide configured to deliver light from a light source to a media-facing surface of the recording head. A near-field transducer is at the media-facing surface the proximate the waveguide. The near-field transducer includes a plasmonic structure with at least two opposing internal surfaces. A dielectric material fills a region between the at least two opposing internal surfaces. A dielectric slit extends between the at least two opposing internal surfaces. The dielectric slit is substantially parallel to the media-facing surface and includes a transparent material with a refractive index different than that of the dielectric material.”

The patent application was filed on June 12, 2018 (16/006,324).

Laser diode with integrated temperature control unit for HAMR device
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,283,151) developed by Wessel, James Gary, Savage, MN, and Olson, Scott Eugene, Eagan, MN, for a “laser diode with integrated temperature control unit for a heat-assisted magnetic recording device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus comprises a first electrical contact, a second electrical contact, and a semiconductor device disposed between the first and second electrical contacts. The semiconductor device comprises a laser diode and a temperature control unit. The laser diode comprises p-type semiconductor material and n-type semiconductor material. The temperature control unit comprises p-type semiconductor material, n-type semiconductor material, and a resistor coupled to the laser diode. One of the p-type semiconductor material and the n-type semiconductor material is shared by the laser diode and the temperature control unit.”

The patent application was filed on March 23, 2018 (15/933,721).

Delete command queue
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,282,103) developed by Stone, Chris Randall, Elgin, TX, Nemawarkar, Shashank, Sundararaman, Balakrishnan, and Peet, Charles Edward, Austin, TX, for “method and apparatus to delete a command queue.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.”

The patent application was filed on April 28, 2016 (15/141,744).

Automated and accurate high-throughput slider-level flatness inspection
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,281,268) developed by Chen, Zhiyu, Eagan, MN, Habermas, Andrew D., Loken, Kurtis Dean, Bloomington, and MN, Kunkel, Gary J., Minneapolis, MN, for “automated and accurate high-throughput slider-level flatness inspection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method includes receiving an image of a surface of a slider bar from an interferometer, where the slider bar includes at least two sliders, and where the image includes image data according to at least two image data channels for a slider bar surface and the at least two sliders. The method also includes generating a slider bar map of the surface of the slider bar based upon the image data of the image, where the slider bar map includes at least two data channels and ascertaining a plurality of individual slider surface maps based on a number of sliders included on the slider bar, where the ascertaining is also based upon the slider bar map having the at least two data channels. The method also includes segmenting the slider bar map according to the plurality of individual slider surface maps.”

The patent application was filed on April 20, 2018 (15/958,646).

Preamble defect detection and mitigation
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,277,718) developed by Bellorado, Jason Vincent, and Marrow, Marcus, San Jose, CA, for “preamble defect detection and mitigation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.”

The patent application was filed on November 22, 2016 (15/359,591).

Read retry operations with estimation of written data based on syndrome weights
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,276,247) developed by Alhussien, AbdelHakim S., San Jose, CA, Sankaranarayanan, Sundararajan, Fremont, CA, Nguyen, Thuy Van, Hanoi, Vietnam, Danjean, Ludovic, and Haratsch, Erich F., San Jose, CA, for “read retry operations with estimation of written data based on syndrome weights.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages, obtaining a syndrome weight for each of the readings of the codeword, identifying a given reading of the codeword having a substantially minimum syndrome weight, and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to, (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or, (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.”

The patent application was filed on July 8, 2016 (15/205,654).

Adaptive read threshold voltage tracking
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,276,233) developed by Danjean, Ludovic, San Jose, CA, Sankaranarayanan, Sundararajan, Fremont, CA, and Haratsch, Erich F., San Jose, CA, for an “adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time, shift the plurality of read reference voltages using the at least one reference voltage offset, and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.”

The patent application was filed on October 31, 2017 (15/799,484).

Data storage device filter
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,276,216) developed by Zhang, Lihong Maruti, Liu, Xiong,and Sun, Hao, Singapore, Singapore, for a “data storage device filter.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A breather filter for reducing water in a data storage device housing includes an outer layer, an inner layer, and an intermediary layer positioned between the inner and outer layers. The outer layer includes an outer layer of hydrophilic material. The inner layer includes at least one of an inner layer of hydrophobic material and an inner layer of hydrophilic material. The intermediary layer includes a water adsorbing material, and fibers that promote water permeation from the inner layer to the outer layer.”

The patent application was filed on September 14, 2017 (15/704,492).

Data storage device fastener seal system
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,276,215) developed by Su, Ying, Yap, Pow Ming, Singapore, SG, Cho, Kok Liang, Melaka, MY, and Lee, Chee Xian, Singapore, Singapore, for a “data storage device fastener seal system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device fastener seal system can have at least a base, a cover, and a fastener seal. The base may have at least one fastener aperture and a first contact surface while the cover can have a second contact and a fastener hole. The second contact surface may physically contact the first contact surface to enclose a data storage region. The fastener seal can be positioned between the base and cover proximal the fastener aperture with the fastener seal extending less than an inch from the fastener aperture in every direction along a plane parallel to the first and second contact surfaces.”

The patent application was filed on December 4, 2017 (15/830,087).

Parallelized writing of servo RRO/ZAP fields
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,276,197) developed by Bellorado, Jason, and Marrow, Marcus, San Jose, CA, for a “parallelized writing of servo RRO/ZAP fields.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.”

The patent application was filed on October 25, 2017 (15/793,864).

Managing multiple namespaces in non-volatile memory, NVM
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,275,361) developed by Ish, Mark, Sandy Springs, GA, Williams, Steven S., Longmont, CO, and Munsil, Jeffrey, Fort Collins, CO, for “managing multiple namespaces in a non-volatile memory, NVM.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and method for managing namespaces in a Non-Volatile Memory Express, (NVMe) controller environment. A non-volatile memory, (NVM) is arranged to store map units, (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address, (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.”

The patent application was filed on May 31, 2017 (15/609,758).

Save critical data upon power loss
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,275,166) developed by Shen, Jin Quan, Chng, Yong Peng, Zaw, Thein Than, and Hartono, Robertus, Singapore, Singapore, for a “save critical data upon power loss.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for saving critical data upon power loss are described. In one embodiment, the systems and methods include performing a write operation to a first track of a storage drive, monitoring a voltage level of a storage drive to detect power loss on the storage drive while performing the write operation, identifying a track ID of a second track adjacent to the first track upon detecting power loss on the storage drive, and storing the identified track ID in a non-volatile memory on the storage drive.”

The patent application was filed on May 4, 2018 (15/971,588).

Random time generated interrupts in cryptographic hardware pipeline circuit
Seagate Technologies LLC, Cupertino, CA, has been assigned a patent (10,270,586) developed by Moss, Robert W., Windsor, CO, for a “random time generated interrupts in a cryptographic hardware pipeline circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and method for defending against a side-channel information attack such as a differential power analysis, (DPA) attack. In some embodiments, a cryptographic hardware pipeline circuit performs a selected cryptographic function upon a selected set of data over a processing time interval. The pipeline circuit has a sequence of stages connected in series. The stages are enabled responsive to application of an asserted enable signal. An enable interrupt circuit is configured to periodically interrupt the selected cryptographic function to provide a plurality of processing intervals interspersed with the interrupt intervals. At least a selected one of the processing intervals or the interrupt intervals have random durations selected responsive to a series of random numbers.”

The patent application was filed on April 25, 2017 (15/496,060).