Cadence Design Systems Assigned Patent

Cadence Design Systems, Inc., San Jose, CA, has been assigned a patent (10,275,306) developed by MacLaren, John, Olson, Carl, Austin, TX, Johnson, Jerome J., and Shepherd, Thomas J., Cedar Park, TX, for “system and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word’s data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word’s data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.”

The patent application was filed on February 9, 2017 (15/428,719).