Western Digital Assigned Seventeen Patents

Half select method and structure for gating Rashba or spin Hall MRAM
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,276,782) developed by Braganca, Patrick M., San Jose, CA, and Garcia, Andrei Gustavo Fidelis, Palo Alto, CA, for a “half select method and structure for gating Rashba or spin Hall MRAM.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure generally relates to SHE-MRAM memory cells. A memory cell array comprises one or more memory cells, wherein each of the one or more memory cells comprises a gate electrode, an insulating layer, a spin orbit material electrode, a MTJ, and a top electrode parallel to the gate electrode. The gate electrode and the top electrode are perpendicular to the spin orbit material electrode. By applying a voltage to the gate electrode, passing a current along the spin orbit material electrode, and utilizing Rashba and/or spin Hall effects, writability of select memory cells is enhanced, allowing for individual memory cells to be written upon without disturbing neighboring memory cells. Additionally, Rashba and/or spin Hall effects in neighboring memory cells may be suppressed to ensure only the selected memory cell is written.”

The patent application was filed on October 6, 2016 (15/286,748).

Data storage device coding out ambiguity in three-dimensional magnetic recording
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,276,208) developed by Bai, Zhigang, Fremont, CA, Wei, Yaguang, Pleasanton, CA, Lok Lam, Terence Tin, Cupertino, CA, Ho, Kuok San, Emerald Hills, CA, and Guan, Lijie, Cupertino, CA, for a “data storage device coding out ambiguity in three-dimensional magnetic recording.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk surface comprising a first magnetic recording layer and a second magnetic recording layer. Data is encoded into a codeword comprising a plurality of non-binary symbols wherein each symbol represents one of a plurality of symbol values comprising a first symbol value, a second symbol value, and a third symbol value. The first symbol value is written to the disk surface by magnetizing the first and second magnetic recording layers, and the second symbol value is written to the disk surface by magnetizing the first magnetic recording layer without substantially affecting the magnetization of the second magnetic recording layer. The encoding into the codeword codes out at least one sequence of symbol values to prevent an ambiguity between detecting the first symbol value and the second symbol value during a read operation.”

The patent application was filed on May 25, 2018 (15/990,468).

HAMR medium with rhodium or rhodium-based alloy heat-sink layer
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,276,202) developed by Jubert, Pierre-Olivier, San Jose, CA, Yuan, Hua, San Ramon, CA, and Dorsey, Paul Christopher, Los Altos, CA, for a “heat-assisted magnetic recording, (HAMR) medium with rhodium or rhodium-based alloy heat-sink layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A heat-assisted magnetic recording, (HAMR) medium has a rhodium, (Rh) or Rh-based alloy heat-sink layer. The Rh or Rh-based alloy does not roughen when annealed and thus does not require an intermediate layer between it and the MgO seed layer for the recording layer, so the MgO seed layer can be formed directly on and in contact with the Rh or Rh-based alloy heat-sink layer. The Rh or Rh-based alloy heat-sink layer is formed on a seed layer or multilayer that allows the Rh or Rh-based alloy to grow with the desired face-centered-cubic, (fcc) crystalline structure.”

The patent application was filed on April 23, 2018 (15/959,358).

Split-shaft pivot with interface spacer for dual-actuator HDD
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,276,194) developed by Keshavan, Manoj, and Park, Jung-Seo, San Jose, CA, for a “split-shaft pivot with interface spacer for a dual-actuator hard disk drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A split-shaft pivot assembly for a dual-actuator data storage device may include a first pivot shaft around which a first bearing assembly is affixed, a second pivot shaft around which a second bearing assembly is affixed, and whereby the two pivot shafts are coupled together by way of an interface spacer between the shafts. The interface spacer may include a receiving structure at each end of a housing, for receiving an end of a respective shaft, and an annular slot circumscribing the housing between the receiving structures, where an elastomeric damper is positioned within the slot. The interface spacer housing may be composed of a material having a lower elastic modulus than the material of which the shafts are composed, thereby making the interface spacer relatively compliant. Such features may serve to inhibit and/or damp transmission of vibrational energy among the actuators through the shared split-shaft.”

The patent application was filed on June 21, 2017 (15/629,100).

Perpendicular magnetic recording medium
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,276,192) developed by Hirotsune, Akemi, Takekuma, Ikuko, and Sayama, Junichi, Kanagawa, Japan, for a “perpendicular magnetic recording medium.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A magnetic recording medium includes an amorphous buffer layer, a hybrid layer including a barrier layer, and a texture control layer. The magnetic recording medium also includes a heat sink layer, an under layer, and a perpendicular recording layer.”

The patent application was filed on July 11, 2013 (13/940,132).

Data buffer pointer fetching for direct memory access
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,275,378) developed by Benisty, Shay, Beer Sheva, Israel, for a “data buffer pointer fetching for direct memory access.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Technology is described herein for operating non-volatile storage. In one aspect, a memory controller fetches pointers to data buffers in host system memory just-in-time. For example, just before the memory system is ready perform a DMA the pointers may be fetched. The data buffer pointers may be NVMe Physical Region Page, (PRP) entries in a PRP list. The same data buffer pointer need not be fetched more than once. For example, responsive to the non-volatile memory system determining that a data buffer pointer might be needed a second time, (e.g., for a different DMA), that data buffer pointer is saved such that it can be re-used. In one aspect, if a DMA does access all of a host data buffer, the pointer to that buffer is saved so that it does not need to be fetched again.”

The patent application was filed on March 7, 2017 (15/452,039).

Cross device redundancy implementation
on high performance direct attached non-volatile storage with data reduction
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,275,376) developed by Narasimha, Ashwin, Skandakumaran, Krishanth, Los Gatos, CA, Karamcheti, Vijay, Palo Alto, CA, and Singhai, Ashish, Los Altos, CA, for an “efficient cross device redundancy implementation on high performance direct attached non-volatile storage with data reduction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains, responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment, allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains, storing the number of data grains and the redundancy data to the memory segment of the grain memory, determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied, and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.”

The patent application was filed on March 2, 2016 (15/058,461).

Provide file system functionality over PCIe interface
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,275,175) developed by Bandic, Zvonimir Z., San Jose, CA, Chu, Frank R., Milpitas, CA, Wang, Qingbo, Irvine, CA, and Le Moal, Damien Cyril Daniel, Tokyo-To, Japan, for “system and method to provide file system functionality over a PCIe interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques for providing file system functionality over a PCIe interface are disclosed. In some embodiments, the techniques may be realized as a method for providing file system functionality over a PCIe interface including receiving from a host device a storage command, specially devised for such a standard protocol, at a PCIe-based device controller, parsing, using at least one computer processor of the PCIe-based device controller, the storage command, traversing, using PCIe-based device controller, one or more portions of file system metadata of an associated storage media device, wherein the PCIe-based device controller is configured to traverse the one or more portions of file system metadata based on the parsed storage command independent of any subsequent communication with the host device, and returning data to the host device.”

The patent application was filed on October 6, 2014 (14/507,572).

Tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,269,400) developed by Braganca, Patrick M., and Read, John C., San Jose, CA, for a “tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments disclosed herein generally relate to a multilayer magnetic device, and specifically to a spin-torque transfer magnetoresistive random access memory, (STT-MRAM) device which provides for a reduction in the amount of current required for switching individual bits. As such, a polarizing reference layer consisting of a synthetic antiferromagnet, (SAF) structure with an in-plane magnetized ferromagnet film indirectly exchange coupled to a magnetic film with perpendicular magnetic anisotropy, (PMA) is disclosed. By tuning the exchange coupling strength and the PMA, the layers of the SAF may both be canted such that either may be used as a tilted polarizer for either an in-plane free layer or a free layer with PMA.”

The patent application was filed on September 6, 2017 (15/696,637).

Data storage device switching disk surfaces to perform seek using spiral track
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,269,385) developed by French, Jr., James B., Whitefish, MT, for a “data storage device switching disk surfaces to perform seek using spiral track.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a first head actuated over a first disk surface comprising a first spiral track written from an outer diameter, (OD) of the first disk surface to an inner diameter, (ID) of the first disk surface, and a second head actuated over a second disk surface comprising a second spiral track written from an ID of the second disk surface to an OD of the second disk surface. A seek operation of the first head over the first disk surface is performed in order to access the first disk surface by reading the second spiral track from the second disk surface, seeking the second head over the second disk surface based on reading the second spiral track, and after seeking the second head over the second disk surface, accessing the first disk surface using the first head.”

The patent application was filed on June 7, 2018 (16/002,357).

Providing secure access to digital storage devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,268,814) developed by Barnes, Edwin D., Lake Forest, CA, for “providing secure access to digital storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for providing secure access to a data storage device. The data storage device may include a touch-sensitive input device, (e.g., a touchscreen, a track pad, a touch pad, etc.). A user may provide touch input, e.g., taps and/or swipes) via the touch-sensitive input device. The data storage device may determine whether the touch input, (e.g., tap/swipe input) is valid and may allow access to the data storage device, (e.g., to non-volatile memory of the data storage device) when the touch input is valid.”

The patent application was filed on December 16, 2015 (14/972,013).

Data storage device including temporary storage locations
Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (10,268,386) developed by Hall, David Robison, Rochester, MN, for a “data storage device including temporary storage locations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device may include non-volatile storage media that includes a long-term storage region divided into a plurality of physical regions and a temporary storage region that includes at least two first tier bins. Each logical block address, (LBA) span of a plurality of LBA spans may be associated with at least one physical region. Each first tier bin may be associated with a respective LBA subset of the plurality of LBA spans that includes at least two LBA spans and less than all LBA spans. The data storage device may also include a processor configured to receive first data having an LBA from a first LBA subset and second data having an LBA from a second LBA subset, and writing the first data to a first bin associated with the first LBA subset and writing the second data to a second bin associated with the second LBA subset.”

The patent application was filed on December 28, 2016 (15/392,760).

Data storage device enclosure
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,261,553) developed by Jenkins, Dean Mitcham, La Canada-Flintridge, CA, and Ryan, Robert P., Mission Viejo, CA, for a “data storage device enclosure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A Data Storage Device, (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.”

The patent application was filed on August 31, 2016 (15/252,501).

Encoding and decoding data using multi-layer integrated interleaved codes
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,256,843) developed by Zhang, Xinmiao, Mercer Island, WA, and Hassner, Martin A., Mountain View, CA, for “systems, methods, and devices for encoding and decoding data using multi-layer integrated interleaved codes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.”

The patent application was filed on August 7, 2017 (15/671,141).

Data storage device and method of operation using multiple security protocols
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,255,200) developed by Vichodes, Lev, Beer-Sheva, Israel, and Zankovich, Artsiom, San Jose, CA, for “data storage device and method of operation using multiple security protocols.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a memory and a controller that is coupled to the memory. The controller includes an authentication engine, an interface, and an encryption engine. The authentication engine is configured to authenticate an accessing device based on a message received from the accessing device. The interface is configured to receive data from the accessing device. The message is associated with a first security protocol that does not specify that the data is to be encrypted. The encryption engine is configured to encrypt the data in accordance with a second security protocol, and the controller is configured to receive, after encrypting the data, a request from the accessing device to operate according to the second security protocol.”

The patent application was filed on October 27, 2015 (14/924,545).

Power management of storage devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,254,985) developed by Geml, Adam Christopher, McCambridge, Colin Christopher, Sanders, Philip James, and Sendelbach, Lee Anton, Rochester, MN, for a “power management of storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method includes obtaining power and performance data for each storage device of a plurality of storage devices, and adjusting, based on the power and performance data for the plurality of storage devices, a power consumption level of a particular storage device of the plurality of storage devices.”

The patent application was filed on March 15, 2016 (15/071,038).

Atomic write command support in SSD
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,254,983) developed by Tomlin, Andrew J., San Jose, CA, Jones, Justin, Burlingame, CA, and Mullendore, Rodney N., San Jose, CA, for an “atomic write command support in a solid state drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages, (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.”

The patent application was filed on March 14, 2017 (15/458,901).