Nature Communications has published an article written by Sandip Mondal, Department of Physics, Indian Institute of Science, Bangalore, 560012, India, Present address: SanDisk (Western Digital Corporation) India Device Design Center, Bangalore, 560103, India, and V. Venkataraman, Department of Physics, Indian Institute of Science, Bangalore, 560012, India.
Device and deep level charge trapping response. a Schematic of device architecture. b Cross-sectional scanning electron microscopy (SEM) image of a typical device (thickness of 139 nm). c (top-panel) Atomic force topography of the surface of the devices. (bottom-panel) Optical image taken with camera of an array of devices. d C–V traces of as prepared (AP), heated at 200 and 600°C respectively (Supplementary Note 2). The heating was done for 1h for each sample. C–V was measured with the up-down DC sweep of ±20 V at a rate of 2 V min−1 on the gate (Gate Bias) of the metal-insulator-semiconductor (MIS) while imposing a small AC with amplitude and frequency of 100 mV and 100kHz, respectively. e Variation of hysteresis window (ΔVFB) as a function of heating temperature. (inset) variation of trap density as a function of heating temperature
Abstract:“Intrinsic charge trap capacitive non-volatile flash memories take a significant share of the semiconductor electronics market today. It is challenging to create intrinsic traps in the dielectric layer without high temperature processing steps. The main issue is to optimize the leakage current and intrinsic trap density simultaneously. Moreover, conventional memory devices need the support of tunneling and blocking layers since the charge trapping dielectric layer is incapable of preventing the memory leakage. Here we report a tunable flash memory device without tunneling and blocking layer by combining the discovery of high intrinsic charge traps of more than 1012 cm−2, together with low leakage current of less than 10−7 A cm−2 in solution derived, inorganic, spin-coated dielectric films which were heated at 200 °C or below. In addition, the memory storage capacity is tuned systematically upto 96% by controlling the trap density with increasing heating temperature.“