Winbond Electronics Assigned Six Patents

Non-volatile semiconductor memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (10,062,440) developed by Ryoo, Pil-Sang, and Ho, Wen-Chiao, Taichung, Taiwan, for a “non-volatile semiconductor memory device and reading method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile semiconductor memory device capable of eliminating influence of bit line, (BL) leakage on reading and a reading method thereof. The non-volatile semiconductor memory device includes a memory array, a semiconductor well having a plurality of erase units, and a source switch array having a plurality of source switches. Each of the source switches is coupled to a common source line of one erase unit of the semiconductor well. Only one source switch among the source switches coupled to a selected erase unit among the erase units of the semiconductor well for reading is enabled during a reading operation. Thus, the BL leakage is prevented from affecting the reading operation on memory cells of the memory array, thereby improving the reliability of the non-volatile semiconductor memory device.”

The patent application was filed on June 20, 2017 (15/627,460).

NAND flash memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (10,049,747) developed by Yano, Masaru, Taichung, Taiwan, for “NAND flash memory and program method thereof for suppressing influence of floating gate coupling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.”

The patent application was filed on November 8, 2016 (15/345,521).

Non-volatile semiconductor memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (10,032,512) developed by Senoo, Makoto, Kanagawa, Japan, and Lim, Seow-Fong, San Jose, CA, for a “non-volatile semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements, a selection part, selecting the memory elements of the memory array based on address data, a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value, and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.”

The patent application was filed on July 5, 2017 (15/641,329).

Semiconductor memory device, erasing method and programing
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (10,026,482) developed by Yamauchi, Kazuki, Kanagawa, Japan, for “semiconductor memory device, erasing method and programing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device, an erasing method and a programming method are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings, a page buffer/sensing circuit, which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures, and a detecting circuit, which is connected to the plurality of page buffer/sensing circuits and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.”

The patent application was filed on August 17, 2016 (15/239,763).

Non-volatile semiconductor memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (10,025,707) developed by Sudo, Naoaki, Kanagawa, Japan, for a “non-volatile semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A flash memory includes a memory array including a memory mat MAT-0, MAT-1, a page buffer 170-0, holding data read from the memory mat MAT-0, a page buffer 170-1, holding data read from the memory mat MAT-1, an ECC circuit 140, performing data error checking and correction, an output buffer 110 for outputting data, and a transferring control element, controlling transferring of data between the page buffer 170-0, page buffer 170-1, ECC circuit 140 and output buffer 110. When the memory mat MAT-0 is selected, the transferring control element transfers data held by the page buffer 170-0 to the page buffer 170-1 of the memory mat MAT-1.”

The patent application was filed on September 14, 2017 (15/703,997).

Programming ECC-enabled NAND flash memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (9,971,647) developed by Michael, Oron, San Jose, CA, for “apparatus and method for programming ECC-enabled NAND flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code, (ECC) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.”

The patent application was filed on July 31, 2014 (14/447,919).