Renesas Electronics Assigned Four Patents

Magnetic disk control
Renesas Electronics Corporation, Koutou-ku, Tokyo, Japan, has been assigned a patent (10,056,107) developed by Kurosawa, Minoru, Itagaki, Kichiya, and Ishiji, Seigi, Tokyo, Japan, for a “control device, magnetic disk control system, and control method for controlling disk storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.”

The patent application was filed on September 27, 2017 (15/717,035).

Semiconductor NVDRAM
Renesas Electronics Corporation, Koutou-ku, Tokyo, Japan, has been assigned a patent (10,050,040) developed by Yamakoshi, Hideaki, Tokyo, Japan, for a “semiconductor non-volatile DRAM, (NVDRAM) device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or not to apply the write voltage, (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.”

The patent application was filed on September 19, 2017 (15/709,125).

Semiconductor storage device
Renesas Electronics Corporation, Koutou-ku, Tokyo, Japan, has been assigned a patent (10,049,723) developed by Yabuuchi, Makoto, and Tanaka, Shinji, Tokyo, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.”

The patent application was filed on May 26, 2017 (15/606,903).

Semiconductor storage device
Renesas Electronics Corporation, Koutou-ku, Tokyo, Japan, has been assigned a patent (9,978,445) developed by Sano, Toshiaki, Shibata, Ken, Tanaka, Shinji, Yabuuchi, Makoto, and Maeda, Noriaki, Kanagawa, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix, plural bit-line pairs arranged corresponding to each column of the memory cells, a write driver circuit which transmits data to a bit-line pair of a selected column according to write data, and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring, a first driver circuit which drives the first signal wiring according to a control signal, and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.”

The patent application was filed on December 9, 2016 (15/373,783).