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CEA, CNRS and Université Grenoble Alpes Assigned Patent

Resistive device for memory or logic circuit

Commissariat à l’Energie Atomatique et aux Energies Alternatives (CEA), Paris, France, Centre National de la Recherche Scientifique (CNRS), Paris, France, and Université Grenoble Alpes, Grenoble, France, has been assigned a patent (10,056,266) developed by Dieny, Bernard, Lans en Vercors, France, Darnon, Maxime, Pavezin, France, Navarro, Gabriele, Grenoble, France, and Joubert, Olivier, Meylan, France, for a “method for manufacturing a resistive device for a memory or logic circuit.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate, forming an etching mask on the first conductive layer, etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another, and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate, and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

The patent application was filed on October 15, 2015 (15/520,132).

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