R&D: Coding for Write Latency Reduction in MLC Phase Change Memory

IEEE Transactions on Computers has published an article written by Fabrizio Lombardi, Electrical and Computer Engineering, Notheastern University, Boston, Massachusetts United States 40125, and Kazuteru Namba, Graduate School of Engineering, Chiba University, Chiba, Chiba Japan.

Abstract: “This paper presents a new write latency reduction scheme for a Phase Change Memory (PCM) made of Multi-Level Cells (MLCs). This scheme improves over an existing scheme found in the technical literature and known as CABS. The proposed scheme is based on the utilization of a new coding arrangement for the selection of candidate codewords. The code relies on the two-step feature found in the write operation of a MLC PCM and avoids the symbol that incurs in the largest latency at a higher rate than CABS. A detailed simulation based evaluation and comparison are also pursued; the proposed scheme accomplishes improvements in write latency (for parallel writing) as well as coding rate (15/16 for the proposed scheme versus 15/17 for CABS for 16 symbols or 32-bit word). As the proposed scheme utilizes novel selection criteria for the candidates, the design of the required circuitry (encoder and decoder) has also been changed with respect to CABS; in terms of hardware, the areas of the encoder and decoder for the proposed scheme are reduced by 73% and 56% respectively compared with CABS.“