Micron Assigned Thirteen Patents

Arrays of memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,347) developed by Liu, Jun, and Parekh, Kunal R., Boise, ID, for “arrays of memory cells and methods of forming an array of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.”

The patent application was filed on December 22, 2017 (15/852,275).

Magnetic memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,345) developed by Sugioka, Shigeru, Hiroshima, Japan, for a “magnetic memory device with grid-shaped common source plate, system, and method of fabrication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access lines extending in a column direction and data/sense lines extending in a row direction transverse to the column direction. A common source plate electrically couples magnetic memory cells of the array in both the column direction and the row direction. Electronic systems include such a magnetic memory device operably coupled to a processor, to which at least one input device and at least one output device is operably coupled. Methods of fabricating magnetic memory devices include forming such an array of magnetic memory cells including a common source plate.”

The patent application was filed on January 5, 2017 (15/399,509).

Forming memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,302) developed by Juengling, Werner, Meridian, ID, for “methods of forming memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.”

The patent application was filed on December 27, 2016 (15/391,604).

Data path integrity verification in memory devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,070) developed by Grunzke, Terry, Boise, ID, for a “data path integrity verification in memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.”

The patent application was filed on June 17, 2013 (13/919,135)..

Backup sequence using three transistor memory cell devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,053) developed by Sakui, Koji, Tokyo, Japa, and Feeley, Peter, Boise, ID, for “methods for backup sequence using three transistor memory cell devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods for a backup sequence includes reading first data from a first data memory to a page buffer, copying the first data from the page buffer to a backup page comprising three transistor memory cell devices, erasing the first data memory, programming the first data from the page buffer to a second data memory, and erasing the backup page.”

The patent application was filed on August 14, 2017 (15/675,836).

Data storage with data randomizer in multiple operating modes
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,014,051) developed by Thomson, Preston A., Boise, ID, Zhang, Peiling, El Dorado Hills, CA, and Chen, Junchao, Singapore, Singapore, for a “data storage with data randomizer in multiple operating modes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.”

The patent application was filed on April 18, 2017 (15/490,316).

Phase change memory cell
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,008,664) developed by Liu, Jun, and Violette, Michael P., Boise, ID, for a “phase change memory cell with constriction structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.”

The patent application was filed on March 7, 2016 (15/063,238).

Memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,008,541) developed by Sills, Scott E., and Ramaswamy, Durai Vishak Nirmal, Boise, ID, for “memory arrays and methods of forming an array of memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.”

The patent application was filed on January 12, 2016 (14/993,306).

Memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,008,504) developed by Juengling, Werner, Meridian, ID, for “memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. Each channel region extends from a first source/drain region to a second source/drain region. The channel regions within each row of fins include first channel regions and second channel regions. Wordline configurations extend along the rows of fins. Each wordline configuration has a first wordline component operated in tandem with a second wordline component. The first wordline components electrically couple with only the first channel regions and the second wordline components electrically couple with only the second channel regions.”

The patent application was filed on December 27, 2016 (15/391,138).

Memory devices which include memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,008,503) developed by Juengling, Werner, Meridian, ID, for a “memory devices which include memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.”

The patent application was filed on December 27, 2016 (15/390,959).

Data storage management
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,007,428) developed by Piekarski, Marek, Macclesfield, Great Britain, for a “data storage management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch, receiving an indication of a plurality of logical disks, each logical disk being provided by a respective one of the plurality of storage devices. Each logical disk comprises a plurality of logical blocks. Data representing a virtual disk is generated, the virtual disk comprising a plurality of virtual blocks, each virtual block being provided by a logical block. Access is provided to the virtual disk to a second device different to the first device. A first virtual block is selected, the first virtual block being provided by a first logical block, and a re-mapping operation is performed after which the first virtual block is provided by a second logical block different to the first logical block.”

The patent application was filed on August 16, 2013 (13/969,402).

FeRAM-DRAM hybrid memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,002,666) developed by Kajigaya, Kazuhiko, Saitama, Japan, for a “FeRAM-DRAM hybrid memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.”

The patent application was filed on July 31, 2017 (15/664,546).

Enhancing nucleation in phase-change memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (9,990,989) developed by Pirovano, Agostino, Milan, Italy, Pellizzer, Fabio, Boise, ID, Conti, Anna Maria, Milan, Italy, Fugazza, Davide, Sunnyvale, CA, and Kalb, Johannes A., Beaverton, OR, for an “enhancing nucleation in phase-change memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory, PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.”

The patent application was filed on May 13, 2016 (15/154,410).