Netlist Assigned Four Patents

Non-volatile memory storage for multi-channel memory system
Netlist, Inc., Irvine, CA, has been assigned a patent (9,996,284) developed by Lee, Hyun, Ladera Ranch, CA, for a “non-volatile memory storage for multi-channel memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem, (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.”

The patent application was filed on September 2, 2016 (15/255,894).

Flash-DRAM hybrid memory
Netlist, Inc., Irvine, CA, has been assigned a patent (9,928,186) developed by Lee, Hyun, Ladera Ranch, CA, Chen, Chi-She, Walnut, CA, Solomon, Jeffrey C., Milton, Scott H., Irvine, CA, and Bhakta, Jayesh, Cerritos, CA, for a “flash-DRAM hybrid memory module.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module that is couplable to a memory controller hub, (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.”

The patent application was filed on August 31, 2015 (14/840,865).

Redundant backup using non-volatile memory
Netlist, Inc., Irvine, CA, has been assigned a patent (9,921,762) developed by Amidi, Mike Hossein, Lake Forest, CA, Chen, Chi-She, Walnut, CA, Solomon, Jeffrey C., Milton, Scott H., Irvine, CA, and Bhakta, Jayesh, Cerritos, CA, for a “redundant backup using non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.”

The patent application was filed on September 17, 2014 (14/489,281).

Memory module and methods for handshaking with memory controller
Netlist, Inc., Irvine, CA, has been assigned a patent (9,858,218) developed by Lee, Hyun, Ladera Ranch, CA, for a “memory module and methods for handshaking with a memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The interface includes data, address and control signal pins and an output pin in addition to the data, address and control signal pins. The memory module receives a first command from the memory controller via the address and control signal pins, and enters a first mode in response to the first command. The memory module in the first mode responds to at least one initialization sequence, and sends a first output signal via the output pin to indicate a status of the at least one initialization sequence to the memory controller. The memory module enters a second mode in which the memory module performs memory operations including memory read/write operations according to an industry standard. During the read/write operations, the memory module communicates data with the memory controller via the data signal pins in response to second memory commands received via the address and control signal pins. The memory module may output a second output signal related to the read/write operations via the output pin.”

The patent application was filed on April 1, 2016 (15/088,115).