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BitMICRO Assigned Seven Patents

Storage system with distributed ECC capability, Scatter-gather approach for parallel data transfer in mass storage system, queuing of descriptors for multiple flash intelligent DMA engine operation, bit-mapped DMA and IOC transfer, embedded system boot from storage device, network of memory systems, copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory

Storage system with distributed ECC capability
BitMICRO LLC, Reston, VA, has been assigned a patent (
9,996,419) developed by Bruce, Rey H., San Jose, CA, Climaco, Joey B., Bislig, Philippines, and Mateo, Noeme P., Pasig, Philippines, for a “storage system with distributed ECC capability.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code, (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts, the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices, and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

The patent application was filed on May 9, 2015 (14/708,246).

Scatter-gather approach for parallel data transfer in mass storage system
BitMICRO LLC, Reston, VA, has been assigned a patent (9,971,524) developed by Bruce, Ricardo H., Fremont, CA, Santos, Avnher Villar, Antipolo, Philippines, Verdan, Marlon Basa, Paranaque, Philippines, and Villapana, Elsbeth Lauren Tagayo, Las Pinas, Philippines, for a “
scatter-gather approach for parallel data transfer in a mass storage system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.

The patent application was filed on March 17, 2014 (14/217,249).

Queuing of descriptors for multiple flash intelligent DMA engine operation
BitMICRO LLC, Reston, VA, has been assigned a patent (9,952,991) developed by Bruce, Ricardo H., Fremont, CA, Verdan, Marlon B., Paranaque, Philippines, and Jago-on, Rowenah Michelle, Cagayan de Oro, Philippines, for a “
systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer, retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access, (DMA) operation, and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer, a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access, (DMA) operation, and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

The patent application was filed on April 17, 2015 (14/690,339).

Bit-mapped DMA and IOC transfer
BitMICRO LLC, Reston, VA, has been assigned a patent (9,934,160) developed by Ponce, Cyrill C., Malabon, Philippines, Fuentes, Marizonne Operio, Leyte, Philippines, and Noble, Gianico Geonzon, Laguna, Philippines, for a “
bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA transfer.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention provides the data flow communication control between the source, (flash/IO) and destination, (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core’s descriptors.sup.1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash and IO bus is ongoing.

The patent application was filed on July 22, 2016 (15/217,947).

Embedded system boot from storage device
BitMICRO LLC, Reston, VA, has been assigned a patent (9,934,045) developed by Manlapat, Alvin Anonuevo, San Fernando, Philippines, and Beleno, Ian Victor Pasion, Quezon, Philippines, for an “
embedded system boot from a storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment of the invention, an apparatus comprises an embedded system comprising: a processor configured to execute firmware, a random access memory, (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM, a power-on reset, (POR) sequencer configured to control a boot process of the embedded system, a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory, a direct memory access, (DMA) controller configured initiate and track data transfers, and a configuration and status register, (CSR) controller configured to access modules in the embedded system.

The patent application was filed on April 12, 2015 (14/684,399).

Network of memory systems
BitMICRO LLC, Reston, VA, has been assigned a patent (9,875,205) developed by Bruce, Ricardo H., Fremont, CA, Espuerta, Jarmie De La Cruz, Bacolod, Philippines, and Verdan, Marlon Basa, Paranaque, Philippines, for a “
network of memory systems.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.

The patent application was filed on March 17, 2014 (14/217,161).

Copying of power-on reset sequencer descriptor
from nonvolatile memory to random access memory

BitMICRO LLC, Reston, VA, has been assigned a patent (9,858,084) developed by Manlapat, Alvin Anonuevo, San Fernando, Philippines, and Beleno, Ian Victor Pasion, Quezon, Philippines, for a “
copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “IA mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset, (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors, (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers. Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.

The patent application was filed on March 17, 2014 (14/217,399).

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