Avago/Broadcom Assigned Eight Patents

Network-displaced direct storage
Avago Technologies General IP/Broadcom Ltd., (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,967,340) developed by Hendel, Ariel, Cupertino, CA, and Kishore, Karagada Ramarao, Saratoga, CA, for a “network-displaced direct storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations, (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.”

The patent application was filed on April 9, 2014 (14/248,751).

Fast decoding of data stored in flash memory
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,954,558) developed by Steiner, Avi, Kiriat Motzkin, Israel, Segal, Avigdor, Netanya, Israel, and Weingarten, Hanan, Herzelia, Israel, for a “fast decoding of data stored in a flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for fast decoding, the method may include, (a) performing a hard read of a group of flash memory cells to provide hard read data, wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions, (b) hard decoding the hard read data to provide a hard decoding result, wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions, (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data, (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result, and, (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.”

The patent application was filed on March 3, 2016 (15/059,397).

Devices with asymmetric SAS generation support
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,953,005) developed by Varchavtchik, Luiz, Wichita, KS, Kaufmann, Reid A., Andover, KS, and Unrein, Jason A., Wichita, KS, for “devices with asymmetric SAS generation support.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and structure for devices that implement multiple versions of the Serial Attached Small Computer System Interface, (SAS) protocol. One exemplary embodiment comprises a SAS device that includes at least one physical link, (PHY) that supports a specified generation of SAS protocols, and at least one PHY that supports a different generation of SAS protocols and that does not support the specified generation of SAS protocols. The SAs device also includes an Input/Output,( I/O) processor able to select a PHY to service a SAS connection, based on the generation of SAS protocols supported by the PHY.”

The patent application was filed on February 17, 2015 (14/624,333).

Split flash memory management between host and storage controller
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,921,954) developed by Sabbag, Erez, Kiryat Tivon, Israel, and Weingarten, Hanan, Hertzelia, Israel, for a “method and system for split flash memory management between host and storage controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A computer readable medium, a system and a method for flash memory device that my store instructions for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device, receiving, from the host computer, a second command that is indicative of a manner in which at least one entity out of, (a) memory management metadata, (b) the first data unit and, (c) at least one other data unit, should be stored in the flash memory device, and programming the at least one entity in the flash memory device in response to the second command.”

The patent application was filed on August 27, 2012 (13/595,848).

Data replication across host systems via storage controller
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,921,753) developed by Samanta, Sumanesh, Bangalore, India, Bert, Luca, Cumming, GA, and Krishnamurthy, Naveen, Bangalore, India, for a “data replication across host systems via storage controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments herein provide for redundant data storage. One storage system includes first and second host systems each comprising a memory and a persistent storage device. The storage system also includes first and second storage controllers each comprising a memory, (e.g., DRAM). The memory of the first storage controller is mapped to the memory of the first host system and the memory of the second storage controller is mapped to the memory of the second host system. The first storage controller is operable to DMA data from the persistent storage device of the first host system to the memory of the first storage controller, and to direct the second storage controller to DMA the data to the persistent storage device of the second host system via the memory of the second storage controller.”

The patent application was filed on March 23, 2015 (14/666,156).

Storage controller cache memory operations that forego region locking
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,910,798) developed by Simionescu, Horia Cristian, Milpitas, CA, Hoglund, Timothy E., Colorado Springs, CO, Veerla, Sridhar Rao, Pandit, Panthini, Bangalore, India, and Radhakrishnan, Gowrisankar, Colorado Springs, CO, for a “storage controller cache memory operations that forego region locking.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks, RAID) storage controller. The storage controller includes an interface operable to receive Input/Output, (I/O) requests from a host, a Direct Memory Access, (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists, (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.”

The patent application was filed on October 5, 2015 (14/874,998).

High throughput multi-input compression
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,864,549) developed by Yang, Shaohua, San Jose, CA, Fang, Han, Shanghai, CN, Chang, Wu, Santa Clara, CA, and Fitzpatrick, Kelly, Sudbury, MA, for “systems and methods for high throughput multi-input compression.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.”

The patent application was filed on February 29, 2016 (15/057,081).

Flash memory chip processing
Avago Technologies General IP, (Singapore) Pte. Ltd., Singapore, has been assigned a patent (9,851,921) developed by Weingarten, Hanan, Herzelia, Israel, and Sabbag, Erez, Koranit, Israel, for a “flash memory chip processing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value, sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples, defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell, and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.”

The patent application was filed on October 21, 2015 (14/919,558).