EpoStar Electronics Assigned Two Patents

Decoding method, memory storage device and memory control circuit unit
EpoStar Electronics Corp., Hsinchu, Taiwan, has been assigned a patent (9,934,087) developed by Hsiao, Yu-Hua, and Yen, Heng-Lin, Hsinchu County, Taiwan, for a “decoding method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading a target physical unit based on a first read voltage level, performing a first decoding operation, reading an authentication physical unit based on a first candidate voltage level to obtain first assistance data and reading the authentication physical unit based on a second candidate voltage level to obtain second assistance data if the first decoding operation fails, obtaining a first estimation parameter according to the first assistance data and authentication data and obtaining a second estimation parameter according to the second assistance data and the authentication data, determining a second read voltage level according to the first estimation parameter and the second estimation parameter, and reading the target physical unit again based on the second read voltage level. Accordingly, the decoding efficiency may be improved.”

The patent application was filed on June 17, 2016 (15/185,034).

Data transmission method, memory storage device and memory control circuit unit
EpoStar Electronics Corp., Hsinchu, Taiwan, has been assigned a patent (9,933,975) developed by Ngu, Di-Hsien, Hsinchu County, Taiwan, for a “data transmission method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value, performing a first access operation corresponding to the first command on the rewritable non-volatile memory module, and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area, and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.”

The patent application was filed on November 16, 2016 (15/352,590).