STMicroelectronics Assigned Four Patents

Identifying defect in data-storage medium
STMicroelectronics, Inc., Carrollton, TX, has been assigned a patent (9,837,119) developed by Garani, Shayan Srinivasa, San Diego, CA, and Parthasarathy, Sivagnanam, Carlsbad, CA, for an “identifying a defect in a data-storage medium.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.”

The patent application was filed on November 23, 2015 (14/949,328).

Automatic test-pattern generation for memory-shadow-logic testing
STMicroelectronics International N.V., Schiphol, The Netherlands, has been assigned a patent (9,812,219) developed by Kohli, Nishu, Noida, India, for an “automatic test-pattern generation for memory-shadow-logic testing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of a method for automated test pattern generation, (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.”

The patent application was filed on March 6, 2015 (14/640,601).

Memory device with progressive row reading and related reading
STMicroelectronics S.r.l., Agrate Brianza, MB, Italy, has been assigned a patent (9,805,810) developed by Campardo, Giovanni, Bergamo, Italy, and Polizzi, Salvatore, Palermo, Italy, for a “memory device with progressive row reading and related reading method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.”

The patent application was filed on December 21, 2016 (15/387,397).

Memory cell and corresponding device
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (9,754,681) developed by Mirabella, Ignazio Bruno, Scicli, Italy, Pappalardo, Salvatore, Catania, Italy, Ribellino, Calogero, Mascalucia, Italy, and Nicolosi, Alessandro, Dresano, Italy, for a “memory cell and corresponding device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.”

The patent application was filed on March 1, 2017 (15/446,909).