HGST/WD Assigned Six Patents

Forming PCM and RRAM 3-D memory cells
HGST, Inc., San Jose, CA, a Western Digital Corporation brand, has been assigned a patent (9,837,472) developed by Shepard, Daniel Robert, North Hampton, NH, for a “method for forming PCM and RRAM 3-D memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory, (PCM) and resistive RAM, ReRAM or (RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.”

The patent application was filed on January 23, 2017 (15/412,566).

Library for management of storage devices
HGST Netherlands B.V., Amsterdam, The Netherlands, a Western Digital Corporation brand, has been assigned a patent (9,836,427) developed by Vaishnav, Yatindra, Milpitas, CA, for a “library for seamless management of storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An approach for using a storage library to translate commands from one command language into a different command language. The approach includes receiving a storage request in a command language from an application. The storage request is directed to a target storage device that uses a different command language. The storage request is translated into the different command language of the target storage device using a storage library of command languages and the storage request is performed.”

The patent application was filed on December 29, 2015 (14/983,308).

Incremental error detection and correction for memories
HGST, Inc., San Jose, CA, a Western Digital Corporation brand, has been assigned a patent (9,819,365) developed by Shepard, Daniel R., North Hampton, NH, for an “incremental error detection and correction for memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.”

The patent application was filed on July 19, 2015 (14/803,091).

Embedded non-volatile memory
HGST, Inc., San Jose, CA, a Western Digital Corporation brand, has been assigned a patent (9,812,503) developed by Shepard, Daniel R., North Hampton, NH, Apodaca, Mac D., San Jose, CA, Trent, Thomas Michael, Tucson, AZ, and Hsu, James Juen, Saratoga, CA, for an “embedded non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process, (i) after the MOS transistors’ gate oxide is formed and the gate poly-silicon is deposited, thereby protecting the delicate surface areas of the MOS transistors) and, (ii) before the salicided contacts to those MOS transistors are formed, thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, (prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.”

The patent application was filed on August 15, 2016 (15/236,600).

Repair-optimal parity code
HGST Netherlands B.V., Amsterdam, The Netherlands, a Western Digital Corporation brand, has been assigned a patent (9,793,922) developed by Mateescu, Robert, Pamies-Juarez, Lluis, and Guyot, Cyril, San Jose, CA, for a “repair-optimal parity code.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data.”

The patent application was filed on September 25, 2015 (14/865,388).

3-D planes memory
HGST, Inc., San Jose, CA, a Western Digital Corporation brand, has been assigned a patent (9,679,946) developed by Shepard, Daniel R., North Hampton, NH, for a “3-D planes memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers, (WLs) but also for the opposite polarity common layer, (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM, (e.g., RRAM, ReRAM and Memresistors).”

The patent application was filed on August 25, 2015 (14/835,642).