Toshiba Memory Corporation Assigned Seven Patents

Storage device and server
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,811,489) developed by Suto, Hiroyuki, Kamakura Kanagawa, Japan, for a “storage device and server device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a storage device includes a memory, a controller, an interface unit, a switch, and a switch control unit. The memory stores data. The controller is configured to control writing of data to the memory and reading of data from the memory. The interface unit includes a first terminal, a second terminal, and a third terminal. The first terminal has an electrical status different between a case where the storage device and a first device are connected, and a case where the storage device and a second device are connected. Through the second terminal, voltage is applied by the first device to the storage device in the case where the storage device and the first device are connected, and a control signal is input from the second device to the storage device in the case where the storage device and the second device are connected. Through the third terminal, power is supplied to the storage device. The switch switches a connection status and a disconnection status. In the connection status, the third terminal and the controller are electrically connected. In the disconnection status, the third terminal and the controller are electrically disconnected. The switch control unit is configured to control the switch to switch the connection status and the disconnection status based on electrical statuses of the first terminal and the second terminal.”

The patent application was filed on August 12, 2015 (14/824,418)

Data transfer, and non-transitory computer readable medium
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,811,410) developed by Goto, Masataka, Yokohama, Japan, Murakami, Eimi, Suginami, Japan, Akiyama, Haruhiko, Koganei, Japan, and Sasaki, Tatsuya, Ota, Japan, for a “data transfer device, data transfer method, and non-transitory computer readable medium.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a data transfer device that communicates with a communication device via a network, the storage controller controls reading data from and writing data to a plurality of storages. The correspondence information manager manages correspondence information manager to manage correspondence information between data written by the storage controller and a storage to which the data is written. The storage manager manages an invalid storage being a storage that the storage controller failed to read or write data. The communicator receives an acquisition request message for data from the communication device. The specifier specifies a storage storing the data requested, according to the correspondence information. The reader requests the storage controller to read the data from the storage specified by the specifier when the storage does is not the invalid storage, and not to request the storage controller to read the data when the storage is the invalid storage.”

The patent application was filed on March 16, 2015 (14/658,709).

Memory system and data control
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,811,275) developed by Chen, Ju chen, and Hara, Fumio, Yokohama, Japan, for a “memory system and data control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, in a memory system, a controller is configured to write first data in a page in a block in response to a write request from a host, and update second information used to manage a correspondence between a logical address designated by the write request and a second physical address which is a storage location in the first memory. The controller is configured to perform a first process of updating the first information with the second information and storing the updated information in the first memory. The controller is configured to acquire the first physical address associated to a logical address designated by the write request from the first information. The controller is configured to store, in the first memory, third information including information in which the acquired first physical address and the second physical address are associated.”

The patent application was filed on September 9, 2015 (14/848,853).

Semiconductor storage device and controller
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,811,270) developed by Maejima, Hiroshi, Tokyo, Japan, for a “semiconductor storage device and controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.”

The patent application was filed on October 28, 2016 (15/337,852).

Memory system
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,798,470) developed by Fukuda, Tohru, Nishitokyo Tokyo, Japan, Nakazumi, Shinichiro, and Kojima, Yoshihisa, Kawasaki Kanagawa, Japan, for a “memory system for storing and processing translation information.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.”

The patent application was filed on September 10, 2015 (14/850,387).

Non-volatile memory device
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,793,289) developed by Uechi, Tadayoshi, Kawasaki, Japan, and Kondo, Masaki, Yokkaichi, Japan, for a “non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a conductive layer, a first electrode layer provided side by side with the conductive layer in a first direction, a second electrode layer provided between the conductive layer and the first electrode. At least a part of the second electrode on the conductive layer side has a work function smaller than a work function of the first electrode. The device further includes a first channel body extending through the first electrode layer in the first direction and a charge storage portion provided between the first electrode layer and the first channel body.”

The patent application was filed on November 25, 2015 (14/951,721).

Cache memory for particular data
Toshiba Memory Corporation, Tokyo, Japan, has been assigned a patent (9,792,214) developed by Maeda, Seiji, Kawasaki Kanagawa, Japan, for a “cache memory for particular data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to an embodiment, a cache unit includes: a first memory configured to temporarily hold data and an address of the data, a second memory configured to temporarily hold an address of particular data set in advance, and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.”

The patent application was filed on March 9, 2015 (14/641,827).