Avalanche Technology Assigned Thirteen Patents

Multilayered seed structure for perpendicular MTJ memory element
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,793,319) developed by Gan, Huadong, Fremont, CA, Huai, Yiming, Pleasanton, CA, Yen, Bing K., Cupertino, CA, Malmhall, Roger K., and Zhou, Yuchen, San Jose, CA, for a “multilayered seed structure for perpendicular MTJ memory element.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving multiple layers of a first transition metal with multiple layers of a second transition metal, and a first magnetic layer formed on top of the multilayered seed structure. The first magnetic layer has a multilayer structure formed by interleaving layers of the first transition metal with layers of a magnetic material and has a first fixed magnetization direction substantially perpendicular to a layer plane thereof. The first transition metal is platinum or palladium, while the second transition metal is selected from the group consisting of tantalum, titanium, zirconium, hafnium, vanadium, niobium, chromium, molybdenum, and tungsten.”

The patent application was filed on October 17, 2016 (15/295,002).

Landing pad in peripheral circuit for magnetic random access memory
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,793,318) developed by Satoh, Kimihiro, Fremont, CA, and Huai, Yiming, Pleasanton, CA, for a “landing pad in peripheral circuit for magnetic random access memory, (MRAM).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction, (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein, a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other, and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.”

The patent application was filed on May 19, 2016 (15/158,872).

Programming of non-volatile memory subjected to high temperature exposure
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,793,003) developed by Abedifard, Ebrahim, Chandrasekhar, Uday, Ranjan, Rajiv Yadav, San Jose, CA, and Huai, Yiming, Pleasanton, CA, for a “programming of non-volatile memory subjected to high temperature exposure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions, (MTJs) whose resistance is switchable, and a one-time-programmable, (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.”

The patent application was filed on September 14, 2016 (15/265,774).

LUN management in solid state disk array
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,792,073) developed by Asnaashari, Mehdi, Danville, CA, Nemazie, Siamack, Los Altos Hills, CA, and Shah, Ruchirkumar D., San Jose, CA, for a “method of LUN management in a solid state disk array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of managing logical unit numbers, (LUNs) in a storage system includes identifying one or more LUN logical block address, (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.”

The patent application was filed on February 9, 2015 (14/617,868).

Storage processor managing solid state disk array
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,792,047) developed by Asnaashari, Mehdi, Danville, CA, and Nemazie, Siamack, Los Altos Hills, CA, for a “storage processor managing solid state disk array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of writing to one or more solid state disks, (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.”

The patent application was filed on January 12, 2015 (14/595,170).

Programming of MRAM by boosting gate voltage
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,786,344) developed by Abedifard, Ebrahim, San Jose, CA, and Keshtbod, Parviz, Los Altos Hills, CA, for a “programming of magnetic random access memory, (MRAM) by boosting gate voltage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line, (WL), which is raised to a first voltage, (Vdd), and is then allowed to float. The first voltage and a second voltage, (Vx), are respectively applied to a selected bit line, (BL) coupled to the selected MTJ and a selected source line, (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.”

The patent application was filed on June 5, 2017 (15/614,450).

Magnetic memory element with composite perpendicular enhancement layer
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,780,300) developed by Zhou, Yuchen, San Jose, CA, Yen, Bing K., Cupertino, CA, Gan, Huadong, Fremont, CA, and Huai, Yiming, Pleasanton, CA, for a “magnetic memory element with composite perpendicular enhancement layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is directed to an MTJ memory element comprising a magnetic free layer structure including one or more magnetic free layers that have a variable magnetization direction substantially perpendicular to layer planes thereof, an insulating tunnel junction layer formed adjacent to the magnetic free layer structure, a magnetic reference layer structure including a first magnetic reference layer and a second magnetic reference layer with a perpendicular enhancement layer interposed therebetween, the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof, an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The non-magnetic perpendicular enhancement layer includes a first perpendicular enhancement sublayer formed adjacent to the first magnetic reference layer and a second perpendicular enhancement sublayer formed adjacent to the second magnetic reference layer.”

The patent application was filed on November 30, 2016 (15/365,371).

Perpendicular magnetic memory element having magnesium oxide cap layer
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,748,471) developed by Zhou, Yuchen, San Jose, CA, Wang, Zihui, Milpitas, CA, Gan, Huadong, Fremont, CA, and Huai, Yiming, Pleasanton, CA, for a “perpendicular magnetic memory element having magnesium oxide cap layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure that comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, a first perpendicular enhancement layer, (PEL) formed adjacent to the magnetic free layer structure, a magnetic dead layer formed adjacent to the first PEL, and a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a second PEL. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.”

The patent application was filed on February 23, 2017 (15/440,948).

Pulse programming techniques for voltage-controlled MTJ
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,728,240) developed by Abedifard, Ebrahim, San Jose, CA, and Keshtbod, Parviz, Los Altos Hills, CA, for a “pulse programming techniques for voltage-controlled magnetoresistive tunnel junction, MTJ.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of programming a voltage-controlled magnetoresistive tunnel junction, (MTJ) includes applying a programming voltage pulse, (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.”

The patent application was filed on March 14, 2014 (14/214,064).

De-duplication for SSDs
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,727,245) developed by Nemazie, Siamack, Los Altos Hills, CA, Asnaashari, Mehdi, Danville, CA, Shah, and Ruchirkumar D., San Jose, CA, for a “method and apparatus for de-duplication for solid state disks, (SSDs).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA, (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.”

The patent application was filed on May 26, 2015 (14/722,038).

Fast programming of MRAM
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,691,464) developed by Abedifard, Ebrahim, San Jose, CA, and Keshtbod, Parviz, Los Altos Hills, CA, for a “fast programming of magnetic random access memory, (MRAM).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line, (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line, BL) coupled to the selected MTJ and a selected source line, (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.”

The patent application was filed on January 26, 2017 (15/417,135).

Perpendicular magnetic tunnel junction with in-plane magneto-static switching-enhancing layer
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,679,625) developed by Zhang, Jing, Los Altos, CA, Huai, Yiming, Pleasanton, CA, Ranjan, Rajiv Yadav, Zhou, Yuchen, San Jose, CA, Wang, Zihui, and Hao, Xiaojie, Milpitas, CA, for a “perpendicular magnetic tunnel junction, (pMTJ) with in-plane magneto-static switching-enhancing layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An STTMRAM element includes a magnetic tunnel junction, (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer, (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.”

The patent application was filed on November 2, 2015 (14/930,523).

Implementing MRAM for mobile system-on chip boot
Avalanche Technology, Inc., Fremont, CA, has been assigned a patent (9,658,859) developed by Le, Ngon Van, and Tadepalli, Ravishankar, Fremont, CA, for a “method of implementing magnetic random access memory, (MRAM) for mobile system-on chip boot.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of booting a system on chip, (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory, (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.”

The patent application was filed on November 26, 2013 (14/091,318).