Intel Assigned Ten Patents

Extending capabilities of existing devices
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,753,878) developed by Wang, Randolph Y., Santa Clara, CA, Wei, Shaojun, Liu, Leibo, Tang, Eugene, Song, Jiqiang, Beijing, CN, Chan, Sun, Fremont, CA, Wang, Dawei, Beijing, China, Fang, Jesse, San Jose, CA, Peng, Paul, and Yin, Shouyi, Beijing, China, for a “extending the capabilities of existing devices without making modifications to the existing devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.“

The patent application was filed on November 2, 2011 (13/997,081).

Variable caching structure for managing physical storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,753,856) developed by Abdallah, Mohammad, El Dorado Hills, CA, for a “variable caching structure for managing physical storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.“

The patent application was filed on January 28, 2016 (15/009,684).

Providing rule patterns on grids
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,747,399) developed by Suto, Gyorgy, and Kohlmeier, Aaron B., Hillsboro, OR, for a “method and apparatus for providing rule patterns on grids.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described is a machine-readable storage media having one or more machine executable instructions stored there on that when executed cause one or more processors to perform an operation comprising: define properties of a layout grid, wherein the layout grid provides a three dimensional, (3D) space for organizing a plurality of objects on the layout grid, and define rules for the plurality of objects, wherein the rules define a relationship between the plurality of objects with reference to the defined properties of the layout grid.“

The patent application was filed on September 22, 2015 (14/861,020).

Protecting secure boot process against side channel attacks
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,740,863) developed by Sherman, Brent M., Portland, OR, for a “protecting a secure boot process against side channel attacks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of an invention for protecting a secure boot process against side channel attacks are disclosed. In one embodiment, an apparatus includes cryptography hardware, a non-volatile memory, a comparator, and control logic. The cryptography hardware is to operate during a first boot process. The non-volatile memory includes a storage location in which to store a count of tampered boots. The comparator is to perform a comparison of the count of tampered boots to a limit. The control logic is to, based on the first comparison, transfer control of the apparatus from the first boot process to a second boot process.“

The patent application was filed on November 25, 2014 (14/552,667).

Computing method associated with context-aware management of file cache
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,740,635) developed by Wang, Ren, Portland, OR, Zhao, Weishuang, Pittsburgh, PA, Shen, Wei, Hillsboro, OR, Mesnier, Michael P., Scappoose, OR, Tai, Tsung-Yuan C., and Ergin, Mesut A., Portland, OR, for a “computing method and apparatus associated with context-aware management of a file cache.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device may include a file cache and a file cache manager coupled with the file cache. The file cache manager may be configured to implement a context-aware eviction policy to identify a candidate file for deletion from the file cache, from a plurality of individual files contained within the file cache, based at least in part on file-level context information associated with the individual files. In embodiments, the file-level context information may include an indication of access recency and access frequency associated with the individual files. In such embodiments, identifying the candidate file for deletion from the file cache may be based, at least in part, on both the access recency and the access frequency of the individual files. Other embodiments may be described and/or claimed.“

The patent application was filed on March 12, 2015 (14/656,453).

Communicate timestamp to storage system
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,727,473) developed by Dees, Brian, Hillsboro, OR, Grimsrud, Knut, Forest Grove, OR, and Coulson, Rick, Portland, OR, for a “methods to communicate a timestamp to a storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.“

The patent application was filed on September 30, 2008 (12/286,502).

Power management and monitoring for storage devices
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,727,267) developed by Sebastian, Donia, Fair Oaks, CA, Ramage, Simon D., Vancouver, CA, Gittens, Curtis A., New Westminister, CA, Nelson, Scott, Vancouver, CA, Carlton, David B., Oakland, CA, and Schmidt, Kai-Uwe, Vancouver, CA, for a “power management and monitoring for storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.“

The patent application was filed on September 27, 2016 (15/277,524).

Cloud data storage location monitoring
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,716,756) developed by Li, Hong, El Dorado Hills, CA, Vicente, John B., Roseville, CA, Yarvis, Mark D., and Blakley, James R., Portland, OR, for a “cloud data storage location monitoring.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technologies for monitoring data storage location for cloud data include a cloud monitoring server configured to communicate with one or more cloud customer computing devices and cloud service providers. The cloud monitoring server receives monitoring requests from the cloud customer computing devices and retrieves provider information from the cloud service providers. The cloud monitoring server compiles response data based on the monitoring requests and the provider information, and sends response data to the cloud customer computing devices. Cloud customer computing devices may send on-demand monitoring requests and/or continuous, policy-based monitoring requests. For policy-based monitoring, the cloud monitoring server continually monitors the provider information and provides response data when one or more conditions specified in the policy are satisfied. The cloud monitoring server may also make recommendations and provide feedback based on the monitoring requests or the provider information. Other embodiments are described and claimed.“

The patent application was filed on February 12, 2016 (15/042,214).

Supply-switched dual cell memory bitcell
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,715,916) developed by Tomishima, Shigeki, Portland, OR, for a “supply-switched dual cell memory bitcell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one embodiment, a bit state in a supply-switched dual cell memory bitcell in accordance with the present description, may be read by coupling a supply line to a common node of the bitcell to drive complementary currents through complementary resistance state storage cells for a pair of complementary bit line signal lines of the bitcell. The bit state of the bitcell may be read by sensing complementary bit state signals on the pair of first and second complementary bit line signal lines. In one embodiment, each resistance state storage cell has a resistance state ferromagnetic device such as a magnetic-tunneling junction, (MTJ). In one embodiment, a supply-switched dual cell memory bitcell in accordance with the present description may lack a source or select line, (SL) signal line. Other aspects are described herein.“

The patent application was filed on March 24, 2016 (15/080,563).

Computing method with persistent memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,715,453) developed by Kumar, Sanjay, Hillsboro, OR, Sankaran, Rajesh M., Portland, OR, Dulloor, Subramanya R., Subbareddy, Dheeraj R., Hillsboro, OR, and Anderson, Andrew V., Forest Grove, OR, for a “computing method and apparatus with persistent memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.“

The patent application was filed on December 11, 2014 (14/567,662).