R&D: 40nm Split Gate Embedded Flash Macro With Flexible 2-in-1 Architecture

Code memory with 140MHz read speed and data memory with 1 million cycles endurance

This is a Press Release edited by StorageNewsletter.com on August 22, 2017 at 3:45 pm

2017 Symposium on VLSI Circuits has published an article written by Hung-Chang Yu, Ku-Feng Lin, and Yu-Der Chih, Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, ROC

Abstract: “This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160°C and data storage memory achieves 1M cycles endurance.“