HGST Assigned Eleven Patents

Pogramming multi-level phase change memory, cell based
on actual resistance value and reference resistance value
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,576,655) developed by Eleftheriou, Evangelos S., Pantazi, Angeliki, Papandreou, Nikolaos, Pozidis, Haris, and Sebastian, Abu, Rueschlikon, Switzerland, for a “apparatus and method for programming a multi-level phase change memory, (PCM) cell based on an actual resistance value and a reference resistance value.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus for programming at least one multi-level Phase Change Memory, (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.“

The patent application was filed on October 24, 2012 (13/659,364).

Forming PCM and RRAM 3-D memory cells
HGST, Inc., San Jose, CA, has been assigned a patent (9,570,516) developed by Shepard, Daniel Robert, North Hampton, NH, for a “method for forming PCM and RRAM 3-D memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory, (PCM) and resistive RAM, (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.“

The patent application was filed on December 11, 2015 (14/967,025).

Multi-level phase change device
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,564,585) developed by Lille, Jeffrey, and Franca-Neto, Luiz M., Sunnyvale, CA, for a “multi-level phase change device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.“

The patent application was filed on September 3, 2015 (14/845,016).

MR effect devices having enhanced magnetic anisotropy
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,564,581) developed by Choi, Young-Suk, Los Gatos, CA, Rubin, Kurt Allan, San Jose, CA, and Stewart, Derek, Livermore, CA, for a “magnetoresistive effect devices having enhanced magnetic anisotropy.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.“

The patent application was filed on November 20, 2015 (14/948,145).

Latency command processing for SSD interface protocol
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,563,367) developed by Chu, Frank, Milpitas, CA, Bandic, Zvonimir Z., Vucinic, Dejan, Guyot, Cyril, San Jose, CA, and Wang, Qingbo, Irvine, CA, for a “latency command processing for SSD interface protocol.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing SSDs. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command.“

The patent application was filed on August 26, 2014 (14/469,225).

Hybrid analog and digital memory device
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,558,814) developed by Galinggana, Jr., Roger F., Gregana, James Arnold V., Cabuyao Laguna, Philippines, and Li, Lloyd Henry I., Metro Manila, Philippines, for a “hybrid analog and digital memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell including a floating gate transistor including a floating gate, and an analog sensor element adjacent to the floating gate, where an electrical characteristic of the analog sensor element is affected by an amount of charge on the floating gate.“

The patent application was filed on April 10, 2015 (14/683,850).

Transmission error detector for flash memory controller
HGST Technologies Santa Ana, Inc., Santa Ana, CA, has been assigned a patent (9,543,035) developed by Chen, Tsan Lin, Zhubei, Taiwan, for a “transmission error detector for flash memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks, and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks, determine an origin of the error event, increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error, compare the error count to a threshold value, and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.“

The patent application was filed on March 15, 2012 (13/420,970).

Acknowledgement-less protocol for SSD interface
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,535,870) developed by Vucinic, Dejan, Guyot, Cyril, and Mateescu, Robert, San Jose, CA, for a “acknowledgement-less protocol for SSD interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location, receiving the command from the host, and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.“

The patent application was filed on September 18, 2014 (14/489,881).

Adaptive targeting of read levels in storage devices
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,535,786) developed by Durgam, Aniryudh Reddy, Uppalapati, Haritha, and Yalamanchi, Kiran, San Diego, CA, for a “adaptive targeting of read levels in storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device may include a controller and a plurality of memory devices logically divided into a plurality of pages. Each page in the plurality of pages may include a plurality of bits. The controller may be configured to: apply a read level to a control gate of a transistor for each respective bit in the plurality of bits, determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits, determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value, and adjust, based on the error ratio, the read level.“

The patent application was filed on February 9, 2015 (14/617,231).

Operating flash backed DRAM module
HGST Technologies Santa Ana, Inc., Santa Ana, CA, has been assigned a patent (9,520,191) developed by Moshayedi, Mark, Newport Coast, CA, and Finke, Douglas, Orange, CA, for a “apparatus, systems, and methods for operating flash backed DRAM module.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device includes volatile memory, one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory, an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source, a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory, and the at least one parameter describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the at least one parameter includes serial presence detect information.“

The patent application was filed on February 17, 2015 (14/624,255).

Programming algorithm for improved flash memory endurance and retention
HGST Technologies Santa Ana, Inc., Santa Ana, CA, has been assigned a patent (9,514,823) developed by Melik-Martirosian, Ashot, San Jose, CA, for a “programming algorithm for improved flash memory endurance and retention.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.“

The patent application was filed on July 8, 2015 (14/794,741).