Infinera Assigned Patent

Infinera Corporation, Sunnyvale, CA, has been assigned a patent (9,543,984) developed by Pringle, Scott G., Woodlawn, CA, Karimi, Mehdi, Thomson, Sandy, Ottawa, Canada, and Wu, Yuejian, Woodlawn, CA, for a “efficient storage architecture for low-density parity-check decoding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low-density parity-check, (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.“

The patent application was filed on June 30, 2014 (14/319,503).