GlobalFoundries Assigned Seven Patents

Read only memory with redundancy
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, with applicant IBM Corp., Armonk, NY, has been assigned a patent (9,460,811) developed by Braceras, George M., Essex Junction, VT, Chu, Albert M., Nashua, NH, Gorman, Kevin W., Fairfax, VT, Ouellette, Michael R., Westford, VT, Piro, Ronald A., Essex Junction, VT, Seitzer, Daryl M., Beaverton, OR, Shetty, Rohit, Essex Junction, VT, and Wyckoff, Thomas W., Jeffersonville, VT, for a “read only memory, (ROM) with redundancy.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read only memory, (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.“

The patent application was filed on August 7, 2014 (14/453,779).

Creating OTPROM array possessing multi-bit capacity
with TDDB stress reliability mechanism
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,460,806) developed by Gautam, Akhilesh, and Uppal, Suresh, Clifton Park, NY, for a “method for creating an OTPROM array possessing multi-bit capacity with TDDB stress reliability mechanism.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices, receiving a binary code to program the OTPROM array, separating the binary code into a first part and a second part, programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code, detecting a Idsat level discharged by each device with a multi-bit sense amplifier, and reading the state of each device based on the detected Idsat level.“

The patent application was filed on April 7, 2015 (14/680,228).

Vertical fin eDRAM
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,443,857) developed by Anderson, Brent A., Jericho, VT, Barth, Jr., John E., Williston, VT, and Nowak, Edward J., Essex Junction, VT, for a “vertical fin eDRAM.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.“

The patent application was filed on December 5, 2014 (14/561,999).

Back-gated non-volatile memory cell
GlobalFoundries Singapore Pte. Ltd., Singapore, Singapore, has been assigned a patent (9,444,041) developed by Lim, Khee Yong, Tan, Kian Ming, and Quek, Elgin Kiok Boone, Singapore, Singapore, for a “back-gated non-volatile memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.“

The patent application was filed on December 31, 2013 (14/144,554).

Physically unclonable fuse using NOR type memory array
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,436,845) developed by Iyer, Subramanian S., Mount Kisco, NY, Kirihata, Toshiaki, Poughkeepsie, NY, Kothandaraman, Chandrasekharan, Hopewell Junction, NY, Leu, Derek H., Hopewell Junction, NY, and Rosenblatt, Sami, White Plains, NY, for a “physically unclonable fuse using a NOR type memory array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse, (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code, (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.“

The patent application was filed on March 25, 2014 (14/224,099).

Application-directed memory de-duplication
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,436,614) developed by Dawson, Michael H., Ottawa, Canada, Iyengar, Arun K., Yorktown Heights, NY, and Johnson, Graeme, Ottawa, Canada, for a “application-directed memory de-duplication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a computing system including an application executing on top of a virtualization control layer, wherein the virtualization control layer maps portions of a virtual memory to portions of a physical memory, a method for managing memory including: identifying, by the application, a range of virtual memory whose probability of being replicated in the virtual memory exceeds a given threshold, obtaining, by the application, at least one memory address corresponding to the range of virtual memory, and passing, from the application to the virtualization control layer, an identifier for the range of virtual memory and the memory address corresponding to the range of virtual memory, wherein the identifier is useable by the virtualization control layer to identify similar ranges within the virtual memory.“

The patent application was filed on May 2, 2013 (13/875,702).

Memory system for mirroring data
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,436,563) developed by Chinnakkonda Vidyapoornachary, Diyanesh B., Bangalore, India, Kim, Kyu-hyoun, Mount Kisco, NY, and Tressler, Gary A., Sandy Hook, CT, for a “memory system for mirroring data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system is disclosed, which may include a memory unit of a first type, susceptible to loss of data from corrupting events, and a memory unit of a second type, less susceptible to loss of data from corrupting events than the memory unit of the first type, and a mirrored memory interface, (MMI). The MMI may be coupled to a memory controller, the memory unit of the first type, and the memory unit of the second type. The MMI may, in response to a memory controller write command, receive data from the memory controller and write the data to the memory unit of the first type and to the memory unit of the second type. The MMI may also, in response to a memory controller read command, read data from the memory unit of the first type and send the data to the memory controller.“

The patent application was filed on October 1, 2013 (14/043,110).