Synopsys Assigned Patent
Phase interpolator with phase traversing for delay-locked loop
By Francis Pelletier | October 28, 2016 at 2:34 pmSynopsys, Inc., Mountain View, CA, has been assigned a patent (9,461,655) developed by Boecker, Charles W., Ames, IA, Wang, Alvin, Saratoga, CA, Bottelli, Aldo, Redwood City, CA, and Rao, Chethan, San Jose, CA, for a “phase interpolator with phase traversing for delay-locked loop.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.“
The patent application was filed on June 20, 2013 (14/409,165).
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