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GlobalFoundries Assigned Seven Patents

Implementing reinforcement learning based flash control, backward compatible head for quasi-static tilted reading and/or recording, mechanism of supporting sub-communicator collectives, enhanced data caching and takeover of non-owned storage devices, synchronous mode replication to multiple clusters, optimizing storage utilization by modifying logical volume offset, resistive non-volatile memory

Implementing reinforcement learning based flash control
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,256,371) developed by Franceschini, Michele M., White Plains, NY, Hunter, Hillery C., Chappaqua, NY, Jagmohan, Ashish, Irvington, NY, and Mukundan, Janani, Ithaca, NY, for a “implementing reinforcement learning based flash control.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning, (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations, computes a current system state responsive to the employed feature set, selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action.

The patent application was filed on May 28, 2013 (13/903,182).

Backward compatible head for quasi-static tilted reading and/or recording
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,251,825) developed by Biskeborn, Robert G., Hollister, CA, and Lo, Calvin S., Saratoga, CA, for a “backward compatible head for quasi-static tilted reading and/or recording.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present invention, in some embodiments, relates to magnetic heads having modules with arrays of transducers able to read and/or write while the arrays are positioned at different angles relative to a magnetic medium, thereby enabling reading and/or writing in more than one data storage format. An apparatus according to one embodiment includes a first module having a first array of N+1 transducers, and a second module having a second array of N+1 transducers. Axes of the arrays are oriented about parallel to each other. N of the N+1 transducers of a first array of a first of the modules are about aligned with N of the N+1 transducers of a second array of a second of the modules when the axes of the arrays are tilted at a first angle greater than about 0.1.degree. relative to a line oriented perpendicular to an intended direction of tape travel thereacross.

The patent application was filed on March 11, 2015 (14/645,350).

Mechanism of supporting sub-communicator collectives
with o(64) counters as opposed to one counter for each sub-communicator
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, with applicant International Business Machines Corporation, Armonk, NY, has been assigned a patent (9,244,734) developed by Blocksome, Michael, Kumar, Sameer, Mamidala, Amith R., Yorktown Heights, NY, Miller, Douglas, Rochester, NY, and Ratterman, Joseph D., Seattle, WA, for a “mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a barrier algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table.

The patent application was filed on August 30, 2013 (14/015,098).

Enhanced data caching and takeover of non-owned storage devices
in dual storage device controller configuration with data in write cache
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,239,797) developed by Galbraith, Robert E., Mairet, Dennis C., Rochester, MN, Maitland, Jr., William J., Lenoxville, PA, Tee, Stephen M., Marble Falls, TX, and Weckwerth, Rick A., Oronoco, MN, for a “implementing enhanced data caching and takeover of non-owned storage devices in dual storage device controller configuration with data in write cache.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method, system and computer program product are provided for implementing enhanced data caching and takeover of non-owned storage devices in a computer system. Each of a first controller and a second controller has a cache memory. During normal run-time, each storage device controller validates cached write data after it is written to its cache memory by reading the write data from its cache memory. If any error is detected on the read, then unit check failed storage device controller, which results in a reset of the failed storage device controller. When a storage device controller detects its dual partner controller fails, the surviving storage device controller queues host read/write operations for its storage devices already owned, and tests a cache mirrored copy from its cache memory of the failed first storage device controller before takeover of the failed controller’s storage devices.

The patent application was filed on August 15, 2013 (13/967,633).

Synchronous mode replication to multiple clusters
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,229,829) developed by Beeston, Ralph T., Dawson, Erika M., Tucson, AZ, Johnson, Gavin S., San Jose, CA, Katori, Katsuyoshi, Kanagawa, Japan, and Swingler, Joseph M., Tucson, AZ, for a “synchronous mode replication to multiple clusters.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided are a computer program product, system, and method for synchronous mode replication to multiple clusters receiving a write to a volume from a host. A received write is cached in a memory. A determination is made of a replication rule indicating one of a plurality of replication modes for a first cluster and a second cluster used for replication for the write, wherein one of the replication modes comprises a synchronous mode. A determination is made that the replication rule indicates a synchronous mode for the first and the second clusters. The write is transmitted from the memory to the first cluster to store in a first non-volatile storage of the first cluster and to the second cluster to store in a second non-volatile storage in response to determining that the replication rule indicates the synchronous mode.

The patent application was filed on July 25, 2012 (13/558,274).

Optimizing storage utilization by modifying logical volume offset
GlobalFoundries, Inc., Grand Cayman, Cayman Islands, has been assigned a patent (9,223,510) developed by Aharon, Ofer, Givat Shmuel, Israel, Goldberg, Itzhack, Hadera, Israel, Harony, Shai, Kfar Sava, Israel, and Lechtman, Moriel, Haifa, Israel, for a “optimizing storage utilization by modifying a logical volume offset.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, apparatus and computer program products implement embodiments of the present invention that include arranging a first multiple of storage slices to store a second multiple of logical volumes, and assigning a respective offset to each of the logical volumes. Each of the logical volumes are then configured to start storing data at a first of the storage slices indicated by the assigned respective offset. In operation, data can be stored to a slice indicated by the assigned offset and an internal volume offset. Subsequent to configuring each of the logical volumes, one the storage slices having a highest storage utilization is identified, and one of the logical volumes having a highest number of physical regions in the identified storage slice is reconfigured to start storing the data at a second of the storage slices.

The patent application was filed on June 26, 2013 (13/927,628).

Resistive non-volatile memory
GlobalFoundries Singapore Pte. Ltd., Singapore, has been assigned a patent (9,218,875) developed by Hong, Yang, Poh, Yong Wee Francis, and Chan, Tze Ho Simon, Singapore, Singapore, for a “resistive non-volatile memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.

The patent application was filed on March 14, 2013 (13/802,841).

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