AMD Assigned Patent

Advanced Micro Devices, Inc., Sunnyvale, CA, has been assigned a patent (9,251,069) developed by Eckert, Yasuko, Kirkland, WA, Loh, Gabriel H., Bellevue, WA, Breternitz, Mauricio, O’Connor, James M., Austin, TX, Manne, Srilatha, Portland, OR, Jayasena, Nuwan S., Sunnyvale, CA, and Thottethodi, Mithuna S., West Lafayette, IN, for a “mechanisms to bound the presence of cache blocks with specific properties in caches.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.“

The patent application was filed on October 16, 2013 (14/055,869).