HGST Assigned Thirteen Patents

Atomic write-in-place for hard disk drives
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,236,066) developed by Coker, Jonathan D., Hall, David R., and Thorstenson, Shad H., Rochester, MN, for a “atomic write-in-place for hard disk drives.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In general, techniques are described for writing data to a storage device that comprises an interface and a controller. The interface may receive a request to sequentially write data stored in a first group of tracks to an I-region, where the first group of tracks was also previously written. The controller may move data stored in a second group of consecutive tracks different than the first group of tracks from the I-region to an E-region, the second group having cardinality equal to the tracks that must be moved for the first group to be written sequentially in the I-region. The E-region comprises a portion of the storage device reserved for temporary storage. The controller may determine a position of the I-region where data from one of the second group was previously stored, and write data from the first group of tracks sequentially to the I-region, starting at the position.“

The patent application was filed on January 23, 2015 (14/604,446).

Air bearing surface design with extreme particle trapping holes
for improving HDD particle robustnes
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,230,587) developed by Hu, Yong, San Ramon, CA, Huang, Weidong, Palo Alto, CA, and Tanaka, Katsuhide, Hiratsuka, Japan, for a “air bearing surface design with extreme particle trapping holes for improving HDD particle robustnes.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments disclosed herein generally relate to a head slider within disk drive data storage devices. A head slider comprises a head body having a leading portion on a leading edge and a trailing portion on a trailing edge. The leading portion includes a first leading pad disposed at the MFS and a second leading pad disposed between the first leading pad and the leading edge. The second leading pad is recessed a first vertical distance from the MFS. One or more particle trapping holes are disposed between the first leading pad and the second leading pad. The one or more particle trapping holes are recessed a second vertical distance from the MFS, the second vertical distance being greater than the first vertical distance. Particles encountered by the leading portion may be suctioned into the one or more particle trapping holes, preventing the particles from building-up onto the MFS.“

The patent application was filed on March 6, 2015 (14/640,684).

Error correction with on-demand parity sectors in magnetic storage devices
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,229,813) developed by Chatradhi, Sridhar, San Jose, CA, Hassner, Martin Aureliano, Mountain View, CA, Hwang, Kirk, Palo Alto, CA, and Yamamoto, Satoshi, San Jose, CA, for a “error correction with on-demand parity sectors in magnetic data storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Data storage devices are described with an ECC system that generate additional on-demand ECC information for a previously written track to provide for correction of data errors in the track and thereby avoid having to rewrite the track. Embodiments of the invention address the squeeze-error problem that arises when writing the next, (second) track in a sequence causes errors to be introduced in the adjacent previously written, (first) track. In alternative embodiments the existence of the data errors in the first track can be detected by reading the track or by estimating the number of likely errors using head position data measured while writing the first and second tracks. The additional on-demand ECC information can be written on any track that is available.“

The patent application was filed on March 6, 2014 (14/199,807).

Setting operating parameters for memory cells based
on wordline address and cycle information
HGST Technologies Santa Ana, Inc., Santa Ana, CA, (applicant: STEC, Inc.) has been assigned a patent (9,224,456) developed by Cometti, Aldo G., and Ziperovich, Pablo Alejandro, San Diego, CA, for a “setting operating parameters for memory cells based on wordline address and cycle information.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive’s flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.“

The patent application was filed on May 28, 2015 (14/724,773).

Power arbitration for storage devices
HGST Technologies Santa Ana, Inc., Santa Ana, CA, (applicant: STEC, Inc.) has been assigned a patent (9,223,373) developed by Thakkar, Umang, San Diego, CA, Alavi, Amir, Irvine, CA, Huang, Lun Bin, and Dash, Dillip K., San Diego, CA, for a “power arbitration for storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit, (PAB) are provided.“

The patent application was filed on March 15, 2013 (13/842,101).

Testing data storage systems utilizing micro-transitions
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,218,847) developed by Hanson, Weldon Mark, Rochester, MN, Salo, Michael Paul, San Jose, CA, Taratorin, Alexander, Sunnyvale, CA, and Wood, Roger William, Gilroy, CA, for a “system and method for testing data storage systems utilizing micro-transitions.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of testing a one or more components of a data storage system introduces a first plurality of micro-transitions into a first data write pattern, which is then written to a magnetic media. A read-back signal is generated, and a frequency response of the read-back signal is analyzed to determine performance of the one or more components of the data storage system.“

The patent application was filed on December 18, 2013 (14/132,966).

Storage of data reference blocks and deltas in different storage devices
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,176,883) developed by Yang, Qing, Saunderstown, RI, for a “storage of data reference blocks and deltas in different storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage architecture is composed of an array of a flash memory solid state disk and a hard disk drive or any nonvolatile random access storage that are intelligently coupled by an intelligent processing unit such as a multi-core graphic processing unit. The solid state disk stores seldom-changed and mostly read reference data blocks while the hard disk drive stores compressed deltas between currently accessed I/O blocks and their corresponding reference blocks in the solid state disk so that random writes are not performed on the solid state disk during online I/O operations. The solid state disk and hard disk drive are controlled by the intelligent processing unit, which carries out high speed computations including similarity detection and delta compression/decompression. The architecture exploits the fast read performance of solid state disks and the high speed computation of graphic processing units to replace mechanical operations on hard disk drives while avoiding slow and wearing solid state drive writes.“

The patent application was filed on April 19, 2010 (12/762,993).

Intra-zone wear leveling for HAMR-SMR type storage devices
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,153,290) developed by Bandic, Zvonimir Z., San Jose, CA, Franca-Neto, Luiz M., Sunnyvale, CA, Guyot, Cyril, Manzanares, Adam C., San Jose, CA, Marchon, Bruno, Palo Alto, CA, and Schreck, Erhard, San Jose, CA, for a “intra-zone wear leveling for heat-assisted magnetic recording–shingled magnetic recording, (HAMR-SMR) type storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A head-assisted magnetic recording-shingled magnetic recording, (HAMR-SMR) type storage device is described that includes a control module and one or more magnetic recording layers partitioned into zones. The control module is configured to write initial data beginning at an initial logical address of a zone. The initial logical address of the zone corresponds to an initial physical address of the zone. Responsive to receiving a command from a host associated with the HAMR-SMR type storage device to reset the zone and write subsequent data, the control module is further configured to reset the initial logical address of the zone to a subsequent physical address of the zone, and after resetting the initial logical address, write the subsequent data beginning at the initial logical address of the zone.“

The patent application was filed on January 22, 2015 (14/603,046).

Dampers for actuator assembly of HDD
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,153,261) developed by Kerner, Jeffrey, and Keshavan, Manoj B., San Jose, CA, for a “dampers for actuator assembly of hard disk drive.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An actuator assembly for a magnetic storage device includes a top surface and a bottom surface that opposes the top surface. The actuator assembly also includes a first constraining layer that is secured to the top surface by a first adhesive layer. The first adhesive layer is positioned between the top surface and the first constraining layer. Additionally, the actuator assembly includes a second constraining layer that is secured to the bottom surface by a second adhesive layer. The second adhesive layer is positioned between the bottom surface and the second constraining layer. At least one of, (i) the first constraining layer is configured differently than the second constraining layer, and, (ii) the first adhesive layer is configured differently than the second adhesive layer.“

The patent application was filed on April 4, 2014 (14/245,932).

Far field interference mitigation by relative frequency ordering
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,153,247) developed by Hall, David Robison, Rochester, MN, and Khalili, Ali Sam, Byron, MN, for a “far field interference mitigation by relative frequency ordering.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method is disclosed for improved operation of a data storage device such as a hard disk drive, wherein the overhead for data rewriting is reduced or eliminated by the grouping of logical zones in proximity to other zones with similar writing frequencies. Thus cold zones are written near other cold zones, and hot zones near other hot zones, within a multiplicity of realms on the data storage surface. Substantial reductions in FTI writes are achievable in comparison with previous FTI mitigation algorithms.“

The patent application was filed on January 21, 2015 (14/601,588).

Patterned magnetic storage medium
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (9,142,239) developed by Rubin, Kurt A., San Jose, CA, and Schabes, Manfred E., Saratoga, CA, for a “patterned magnetic storage medium.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a patterned magnetic storage medium is disclosed herein. The magnetic storage medium includes a magnetic domain, a substantially non-magnetic region laterally adjacent to the magnetic domain, and an exchange spring structure disposed between the magnetic domain and the laterally adjacent non-magnetic region wherein the exchange spring structure comprises implanted ions.“

The patent application was filed on December 20, 2011 (13/332,206).

Soft information module
HGST Technologies Santa Ana, Inc., Santa Ana, CA, (applicant : STEC, Inc.) has been assigned a patent (9,136,011) developed by Weathers, Anthony D., Barndt, Richard D.,and Hu, Xinde, San Diego, CA, for a “soft information module.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method for generating reliability information, such as “soft information,” from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level.“

The patent application was filed on March 15, 2013 (13/843,225).

Inter-cell interference algorithms for soft decoding of LDPC codes
HGST Technologies Santa Ana, Inc., Santa Ana, CA, (applicant : STEC, Inc.) has been assigned a patent (9,117,529) developed by Karakulak, Seyhan, Anaraki, Majid Nemati, Weathers, Anthony D., and Barndt, Richard D., San Diego, CA, for a “inter-cell interference algorithms for soft decoding of LDPC codes.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided.“

The patent application was filed on December 21, 2012 (13/725,943).