Ed Doller Board’s Advisor, Nantero

Nantero, Inc. announced the appointment of memory industry executive Edward Doller to its advisory board.

He was previously VP and chief strategist of the NAND solutions group at Micron, where he also served as VP and GM enterprise storage and as VP and chief memory systems architect.

In addition, Nantero also announced that arrays of its new generation of fast, high-density memory (NRAM) were independently tested by Chuo University and the results showing excellent performance and reliability will be presented in a technical paper at the 2015 International Conference on Solid State Devices and Materials (SSDM).

“Ed Doller’s extensive industry experience and deep understanding at both the memory device level and the system level brings a valuable new dimension to our Advisory Board,” said Greg Schmergel, co-founder, CEO and president,  Nantero. “As Nantero’s momentum continues to build and we continue working with multiple customers to bring NRAM to market, we are pleased to see independent validation of our memory’s performance by leading experts such as Professor Takeuchi.“

Doller joined Micron in 2010 via the Numonyx acquisition where he served as VP and CTO after its formation in 2008. Before Numonyx, he spent 15 years at Intel in the flash memory group where he was appointed its CTO in 2004. Prior to Intel, he spent 9 years at IBM in Eat Fishkill, NY and held several key positions all in advanced semiconductor memories. He holds multiple patents, is a co-author of the IEEE floating gate standard, and is a frequent keynote speaker at memory conferences.

“Nantero’s next generation NRAM memory has a unique value proposition that is highly attractive for a variety of applications and end-users, especially those ready to consider how a nonvolatile memory with the speed of DRAM can allow them to rethink their systems architectures,” said Doller. “I am excited to join Nantero’s advisory board and become a part of their world-class team that is working in partnership with multiple industry leaders.”

On Wednesday, September 30th at the SSDM Conference, Dr. Ken Takeuchi of Chuo University and several co-authors will be presenting a paper featuring Nantero’s NRAM titled Investigation of Carbon Nanotube Memory Cell Array Program Characteristics. He is a professor at the department of electrical, electronic, and communication engineering, Faculty of Science and Engineering of Chuo University, and was previously leading Toshiba’s NAND flash memory circuit design for fourteen years. He designed six world’s highest density NAND flash memory products such as 0.7µm 16Mb, 0.4µm 64Mb, 0.25µm 256Mb, 0.16um 1Gb, 0.13µm 2Gb and 56nm 8Gb NAND flash memories. He holds 210 patents worldwide including 109 U.S. patents. With his invention, “multipage cell architecture“, presented at Symposium on VLSI Circuits in 1997, he commercialized the first MLC NAND flash memory in 2001.