Macronix Assigned Three Patents

Low cost scalable 3D memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (9,018,692) developed by Lung, Hsiang-Lan, Dobbs Ferry, NY, for a “low cost scalable 3D memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.“

The patent application was filed on March 23, 2011 (13/070,323).

Fabricating memory device with charge storage layer
at gap located side of gate dielectric underneath the gate
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (9,018,085) developed by Yan, Shih-Guei, Tsai, Wen-Jer, Cheng, Cheng-Hsien, Hsinchu, Taiwan, for a “method of fabricating memory device with charge storage layer at gap located side of gate dielectric underneath the gate.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.“

The patent application was filed on March 5, 2014 (14/198,320).

3D NAND flash memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (9,018,047) developed by Lue, Hang-Ting, Hsinchu, Taiwan, for a “3D NAND flash memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.“

The patent application was filed on September 15, 2014 (14/486,901).