Micron Assigned Three Patents

3D memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,946,807) developed by Hopkins, John, Fan, Darwin Franseda, Boise, ID, Simsek-Ege, Fatma Arzum, Brighten, James, Boise, ID, Mauri, Aurelio Giancarlo, Meda, Italy, and Jayanti, Srikant, Boise, ID, for a “3D memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.“

The patent application was filed on January 24, 2013 (13/748,747).

Protection of security parameters in storage devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,949,626) developed by Asnaashari, Mehdi, Danville, CA, for a “protection of security parameters in storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize operation, data stored on a memory unit in the storage device may be altered prior to communicating an updated partition size to a host computer. In some examples, data is altered prior to storing the updated partition sizes in the storage device. In this manner, a host system may not receive the updated partition sizes until after the data is altered. Altering data may avoid exposure encrypted data, information about one or more security parameters used to encrypt data on the memory unit or decrypt data retrieved from the memory unit, or combinations thereof.“

The patent application was filed on January 23, 2013 (13/747,917).

Fabricating integrated structures and forming vertically-stacked memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,946,076) developed by Simsek-Ege, Fatma Arzum, and Wilson, Aaron R., Boise, ID, for a “methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.“

The patent application was filed on March 15, 2013 (13/835,551).