SanDisk Assigned Eleven Patents

Storage device managing playable content
SanDisk IL Ltd., Kfar Saba, Israel, has been assigned a patent (8,943,409) developed by Bryant-Rich, Donald Ray, Haifa, Israel, Goodman, Daniel Isaac, Beit Shemesh, Israel, and Hahn, Judah Gamliel, Ofra, Israel, for a “storage device managing playable content.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Displaying storage device-generated menus for playback includes connecting a storage device to a host capable of playing back video content, and presenting to the host a root directory through which a content selection file allows selecting video files for playback through user-storage device interaction, and, optionally, one or more service files that provide various useful information that are also playable back through user-storage device interaction. This typically further includes displaying a Main Menu that represents these files and playing Main Menu items as regular video files/contents. While the content selection file is played back, a content selection menu is generated by the storage device and displayed by the host, and each content selection menu item is playable by transmitting a playback command to the storage device rather than to the host. A storage device is also provided, which uses such method.“

The patent application was filed on December 26, 2008 (12/344,401).

Bit line current trip point modulation for reading nonvolatile storage elements
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,942,047) developed by Mui, Man L., Santa Clara, CA, Kamei, Teruhiko, Yokohama, Japan, Dong, Yingda, San Jose, CA, Oowada, Ken, Fujisawa, Japan, Kato, Yosuke, Kamakura, Japan, Ito, Fumitoshi, Yokohama, Japan, and Lee, Seungpil, San Ramon, CA, for a “bit line current trip point modulation for reading nonvolatile storage elements.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.“

The patent application was filed on May 29, 2014 (14/290,891).

Non-volatile storage with process that reduces read disturb on end wordlines
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,942,043) developed by Yuan, Jiahui, Fremont, CA, Lee, Shih-Chung, Yokohama, Japan, Liang, Guirong, Santa Clara, CA, and Chen, Wenzhou, San Jose, CA, for a “non-volatile storage with process that reduces read disturb on end wordlines.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment. the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.“

The patent application was filed on March 4, 2013 (13/783,928).

High endurance nonvolatile memory
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,942,038) developed by Yang, Nian Niles, Mountain View, CA, and Manohar, Abhijeet, Bangalore, India, for a “high endurance nonvolatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.“

The patent application was filed on April 2, 2013 (13/855,579).

Data reprogramming for data storage device
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,942,028) developed by Hu, Xinde, San Diego, CA, for a “data reprogramming for a data storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a non-volatile memory and a controller. A method includes programming information to the non-volatile memory. The information includes multiple codewords. The method further includes accessing a sample codeword of the multiple codewords from the non-volatile memory and determining an error rate associated with the sample codeword. The error rate is determined by an error correcting code, ECC) engine. The method further includes programming the information at the non-volatile memory in response to the error rate satisfying an error threshold.“

The patent application was filed on June 16, 2014 (14/305,386).

Statistical read comparison signal generation for memory systems
Sandisk Enterprise IP LLC, Milpitas, CA, has been assigned a patent (8,938,658) developed by Tai, Ying Yu, Mountain View, CA, and Ma, Yueh Yale, Palo Alto, CA, for a “statistical read comparison signal generation for memory systems.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.“

The patent application was filed on August 31, 2012 (13/602,031).

Data storage device with intermediate ECC stage
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,938,656) developed by Liu, Tao, Santa Clara, CA, for a “data storage device with intermediate ECC stage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a non-volatile memory and a controller including a first error correction coding, ECC) engine configured to generate a first codeword corresponding to data to be stored at the non-volatile memory. The data storage device also includes a second ECC engine coupled to the controller and to the non-volatile memory. The second ECC engine is configured to receive a representation of the first codeword from the controller and to perform a decode operation of the representation of the first codeword to correct transmission errors prior to storage of the data in the non-volatile memory.“

The patent application was filed on September 14, 2012 (13/618,313).

Bit line BL isolation scheme during erase operation for non-volatile storage
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,937,837) developed by Dunga, Mohan Vamsi, Santa Clara, CA, Kim, Kwang-Ho, Milpitas, CA, and Higashitani, Masaaki, Cupertino, CA, for a “bit line BL isolation scheme during erase operation for non-volatile storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.“

The patent application was filed on May 3, 2013 (13/886,852).

Non-volatile storage with read process that reduces disturb
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,937,835) developed by Lei, Bo, San Ramon, CA, Wan, Jun, and Pan, Feng, San Jose, CA, for a “non-volatile storage with read process that reduces disturb.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.“

The patent application was filed on March 4, 2013 (13/783,781).

System and method of communicating command data in master-slave environment
Sandisk Technologies Inc., Plano, TX, has been assigned a patent (8,935,465) developed by Shaharabany, Amir, Kochav Yair, Israel, Oshinsky, Hadas, Kfar Saba, Israel, and Sela, Rotem, Haifa, Israel, for a “system and method of communicating command data in a master-slave environment.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method includes, in a data storage device including a non-volatile memory, performing receiving, from a host device in a master-slave configuration with the data storage device, a first notification corresponding to a first read command. The method also includes storing, based on the first notification, a first entry in a notification queue. The first entry corresponds to the first read command. The method further includes storing first data corresponding to a second command at a location of the non-volatile memory. The location corresponds to an address to be read upon execution of the first read command. The second command is associated with an operation to be performed by the host device. The method includes, after storing the second data, setting an indicator corresponding to the first entry. The set indicator conveys that the data storage device is ready to execute the first read command.“

The patent application was filed on June 16, 2014 (14/305,758).

Compensation scheme for non-volatile memory
Sandisk 3D LLC, Milpitas, CA, has been assigned a patent (8,934,295) developed by Chen, Yingchang, Cupertino, CA, Kalra, Pankaj, San Jose, CA, and Gorla, Chandrasekhar, Cupertino, CA, for a “compensation scheme for non-volatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.“

The patent application was filed on October 4, 2014 (14/506,610).