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Toshiba Assigned Eleven Patents

Storage medium, non-volatile semiconductor memory, adjusting linear recording density and HDD, MRAM, memory system with flush processing from volatile memory, generating write data and readout data, semiconductor memory device, HDD and touchdown determination

Information storage medium, reproducing and recording method
Kabushiki Kaisha Toshiba, Minato-ku, Japan, has been assigned a patent (8,942,077) developed by Ando, Hideo, Hino, Japan, Morita, Seiji, Yokohama, Japan, and Takazawa, Koji, Tokyo, Japan, for a “information storage medium, reproducing method, and recording method.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

The patent application was filed on March 2, 2014 (14/194,782).

Non-volatile semiconductor memory device improving failure-relief efficiency
Kabushiki Kaisha Toshiba, Minato-ku, Japan, has been assigned a patent (8,942,040) developed by Shirakawa, Masanobu, Chigasaki, Japan, for a “non-volatile semiconductor memory device capable of improving failure-relief efficiency.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.

The patent application was filed on July 16, 2013 (13/943,266).

Nonvolatile semiconductor memory device
Kabushiki Kaisha Toshiba, Minato-ku, Japan, has been assigned a patent (8,942,039) developed by Sakurai, Kiyofumi, and Futatsuyama, Takuya, Yokohama, Japan, for a “nonvolatile semiconductor memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series, and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells, and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region.

The patent application was filed on March 15, 2013 (13/839,090).

Adjusting linear recording density and HDD
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,941,942) developed by Sato, Hiroaki, and Tanaka, Hiroyuki, Yokohama, Japan, for a “method for adjusting linear recording density and magnetic disk drive.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, there is provided a method, implemented in a magnetic disk drive, for adjusting a linear recording density. The method obtains a first flying-dependent error sensitivity for each of two or more heads. The first flying-dependent error sensitivity represents a change in read error rate corresponding to a change in flying height of the head during write. In addition, the method reduces the linear recording density of a first recording surface associated with a first head of the two or more heads if the first flying-dependent error sensitivity is a second flying-dependent error sensitivity higher than a threshold and corresponds to the first head.

The patent application was filed on March 15, 2013 (13/835,731).

Magnetic random access memory
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,941,197) developed by Kajiyama, Takeshi, Yokohama, Japan, and Asao, Yoshiaki, Sagamihara, Japan, for a “magnetic random access memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.

The patent application was filed on February 9, 2012 (13/370,075).

Nonvolatile memory with resistance change layer
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,941,088) developed by Takano, Kensuke, Kanagawa-ken, Japan, Ozawa, Yoshio, Kanagawa-ken, Japan, Sekine, Katsuyuki, Mie-ken, Japan, and Wada, Junichi, Kanagawa-ken, Japan, for a “nonvolatile memory with resistance change layer.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A nonvolatile memory device includes: a first conductive layer, a second conductive layer, a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current, and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.

The patent application was filed on September 27, 2013 (14/038,796).

Memory system with flush processing from volatile memory to nonvolatile memory
utilizing management tables and different management units
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,938,586) developed by Yano, Junji, Kanagawa, Japan, Hatsuda, Kosuke, Matsuzaki, Hidenori, Tokyo, Japan, and Kato, Ryoichi, Kanagawa, Japan, for a “memory system with flush processing from volatile memory to nonvolatile memory utilizing management tables and different management units.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes: a cache memory, a nonvolatile semiconductor memory, and a controller. The controller includes a plurality of management tables that manage data stored in the cache memory and the nonvolatile semiconductor memory using a cluster unit and a track unit. The controller performs data flushing processing from the cache memory to the nonvolatile semiconductor memory when the number of track units registered in the cache memory exceeds a predetermined threshold. Data may be flushed to the nonvolatile memory in different size data units such as a cluster or a track. Data flushing processing may also be performed if a last free way is used when data writing processing is performed on the cache memory managed in a set associative system. The nonvolatile semiconductor memory can be a NAND flash memory.

The patent application was filed on February 10, 2009 (12/529,228).

Generating write data and readout data
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,937,844) developed by Asano, Shigehiro, and Hida, Toshikatsu, Kanagawa, Japan, for a “apparatus for generating write data and readout data.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.

The patent application was filed on February 28, 2012 (13/406,945).

Magnetic memory
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,937,832) developed by Kitagawa, Eiji, Yokohama, Japan, Saida, Daisuke, and Shimomura, Naoharu, Tokyo, Japan, for a “magnetic memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a magnetic memory includes a magnetoresistive element. The element includes a first magnetic film having a variable magnetization perpendicular to a film surface, a second magnetic film having an invariable magnetization perpendicular to the film surface, a nonmagnetic film between the first and second magnetic films, a magnetic field application layer including a third magnetic film having a magnetization parallel to the film surface. The third magnetic film applies a magnetic field parallel to the film surface to the first magnetic film. A magnitude of the magnetization of the third magnetic film when supplying a read current is larger than a magnitude of the magnetization of the third magnetic film when supplying a write current.

The patent application was filed on September 18, 2012 (13/621,969).

Semiconductor memory device
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,937,830) developed by Sakamoto, Kei, Nagoya, Japan, Okamura, Takayuki, Yasutake, Nobuaki, Yokkaichi, Japan, and Nishimura, Jun, Kuwana, Japan, for a “semiconductor memory device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value, a silicon oxide film provided on a side surface of the first insulating film, and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.

The patent application was filed on February 27, 2013 (13/778,371).

Magnetic disk apparatus and touchdown determination
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,937,785) developed by Kojima, Shuichi, Kodaira, Japan, for a “magnetic disk apparatus and touchdown determination method.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a magnetic disk apparatus includes a magnetic disk, a slider including a head element, a heater which heats the slider and vary a protrusion amount of the head element toward the magnetic disk, a controller which performs DFH control to vary a control amount for power applied to the heater at a fixed period of time, a sensor which outputs a signal corresponding to the protrusion amount of the head element, and a determination unit which determines a touchdown of contact between the magnetic disk and part of the slider, based on a peak value of a DC output signal of the sensor.

The patent application was filed on March 7, 2014 (14/200,434).

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