Toshiba Assigned Four Patents

Cryptographic apparatus and memory system
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,908,859) developped by Fujisaki Koichi, Kanagawa, Japan, for “cryptographic apparatus and memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a cryptographic apparatus includes: cryptographic cores (cores), an assigning unit, a concatenating unit, and an output controlling unit. If a CTS flag thereof is on, each core encrypts using a symmetric key cipher algorithm utilizing CTS, while using a symmetric key. When an input of a CTS signal is received, the assigning unit assigns first input data to a predetermined core and turns on the CTS flag thereof. The concatenating unit generates concatenated data by concatenating operation data generated during encrypting the first input data, with second input data that is input immediately thereafter. The output controlling unit controls outputting the concatenated data to the predetermined core, outputting first encrypted data obtained by encrypting the concatenated data, and over outputting second encrypted data obtained by encrypting the first input data, and further turns off the predetermined core’s CTS flag.“

The patent application was filed on March 1, 2011 (13/037,710).

Servo demodulation and disk storage apparatus
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,908,303) developped by Yamada Tomoyoshi,Yokohama, Japan, for “method for servo demodulation and disk storage apparatus.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, in a method for servo demodulation, a first demodulated signal and a second demodulated signal, which are calculated from amplitude values of burst signal patterns of a first area and a second area, are generated in order to generate a position error signal of a reader, based on a servo pattern read from a disk by the reader. Further, in the method for servo demodulation, a square-root of sum of squares of the first and the second demodulated signals is calculated, and an optimal compensation coefficient of a linearity correction function to be used in linearity compensation of the position error signal is calculated based on a maximum value and a minimum value of the square-root of sum of squares.”

The patent application was filed on November 15, 2013 (14/081,908).

Method for detecting touchdown of head and disk storage apparatus
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,908,317) developped by Aoyagi Yuka, Yokohama, Japan, Kojima Shuichi, Kodaira, Japan, Watanabe Toru, Kawasaki, Japan for “method for detecting touchdown of head and disk storage apparatus.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, there is provided a method for detecting touchdown of head in a disk storage apparatus. The disk storage apparatus includes the head. The head includes a write element, a read element, a head disk interference (HDI) sensor, and a heater element. The HDI sensor detects thermal interference between the head and the disk. The method supplies alternating-current heater power to the heater element. The method increases the heater power in a step-by-step manner. The method further detects a phase of an output signal from the HDI sensor corresponding to the increased heater power, and detects the touchdown based on a change in the detected phase.”

The patent application was filed on March 12, 2014 (14/206,923).

Resistance change memory
Kabushiki Kaisha Toshiba, Tokyo, Japan, has been assigned a patent (8,907,318) developped by Sonehara Takeshi, Kawasaki, Japan, Okamura Takayuki, Machida, Japan, Shigeoka Takashi, Fujisawa, Japan, and Kondo Masaki, Kawasaki, Japan, for “resistance change memory .”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.”

The patent application was filed on October 31, 2012 (13/665,681).