Micron Assigned Two Patents

Flash storage partial page caching
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,862,860) developed by Viet Ly, San Jose, CA, and Michael Murray, Mountain View, CA, for “flash storage partial page caching.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.”

The patent application was filed on May 26, 2011 (13/116,626).

Multi-level charge storage transistors and associated methods
Micron Technology, Boise, ID, has been assigned a patent (8,859,349) developed by Gurtej S. Sandhu, Boise, and Durai Vishak Nirmal Ramaswamy, Boise, ID, for “multi-level charge storage transistors and associated methods.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.”

The patent application was filed on Jan. 18, 2013 (13/745,452).