IBM Assigned Four Patents

Storage adapter performance optimization with cache data/directory mirroring
IBM Corp., Armonk, NY, has been assigned a patent (8,868,828) developed by 11 co-inventors for “implementing storage adapter performance optimization with cache data/directory mirroring.”

The co-inventors are Brian E. Bakke, Brian L. Bowles, Michael J. Carnevale, Robert E. Galbraith II, Adrian C. Gerhard, Rochester, MN, Murali N. Iyer, Daniel F. Moertl, Mark J. Moran, Minneapolis, MN, Gowrisankar Radhakrishnan, Rochester, MN, Rick A. Weckwerth, Oronoco, MN, and Donald J. Ziebarth, Rochester, MN.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.”

The patent application was filed on May 24, 2011 (13/114,185).

Enabling throttling on average write throughput for SSD
IBM, Armonk, NY, has been assigned a patent (8,868,875) developed by Gary A. Tressler, Sandy Hook, CT, and Andrew D. Walls, San Jose, CA, for “enabling throttling on average write throughput for solid state storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.”

The patent application was filed on March 14, 2013 (13/826,386).

Adaptive prestaging in storage controller
IBM, Armonk, NY, has been assigned a patent (8,874,840) developed by five co-inventors for the “adaptive prestaging in a storage controller.”

The co-inventors are Michael T. Benhase, Nedlaya Y. Francisco, Binny S. Gill, Shrewsbury, MA, Lokesh M. Gupta, and Suguang Li, Tucson, AZ.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one aspect of the present description, at least one of the value of a prestage trigger and the value of the prestage amount, may be modified as a function of the drive speed of the storage drive from which the units of read data are prestaged into a cache memory. Thus, cache prestaging operations in accordance with another aspect of the present description may take into account storage devices of varying speeds and bandwidths for purposes of modifying a prestage trigger and the prestage amount. Other features and aspects may be realized, depending upon the particular application.”

The patent application was filed on March 6, 2013 (13/786,981).

Error detection in mirrored storage system
IBM, Armonk, NY, has been assigned a patent (8,874,958) developed by David A. Gilbert, Manchester, UK, for “error detection in a mirrored storage system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method and system for are provided for error detection in a mirrored data storage system. The method includes a first mirrored system applying a first ECC algorithm and a second mirrored system applying a second error correction code algorithm. The method reads recovered data in each of the first and second mirrored systems and processes the recovered data in each of the first and second mirrored systems by applying both first and second error correction code algorithms to produce four calculated error correction code values. The method uses the calculated error correction code values to determine the correct recovered data of the first and second mirrored systems.”

The patent application was filed on Nov. 3, 2011 (13/288,085).