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SST (Microchip) Assigned Three Patents

Non-volatile memory device with plural reference cells, forming memory cell by reducing diffusion of dopants under gate, power line compensation for flash memory sense amplifiers

Non-volatile memory device with plural reference cells
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (8,780,639) developed by nine co-inventors for a “non-volatile memory device with plural reference cells, and method of setting the reference cells.”

The co-inventors are Xian Liu, Sunnyvale, CA, Michael James Heinz, Livermore, CA, Eugene Jinglun Tam, Saratoga, CA, Michael K. Doan, Milpitas, CA, Alexander Kotov, Sunnyvale, CA, Tho Ngoc Dang, San Jose, CA, Jack Edward Frayer, Boulder Creek, CA, Jung Hee Yun, Fremont, CA, and Thuan T. Vu, San Jose, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

The patent application was filed on May 8, 2012 (13/466,878).

Forming memory cell by reducing diffusion of dopants under gate
Silicon Storage Technology, San Jose, CA, has been assigned a patent (8,785,307) developed by four co-inventors for “a method of forming a memory cell by reducing diffusion of dopants under a gate.”

The co-inventors are Mandana Tadayoni, Cupertino, CA, Chien-Sheng Su, Nhan Do, Saratoga, CA, and Xian Liu, Sunnyvale, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.”

The patent application was filed on Aug. 23, 2012 (13/593,448).

Power line compensation for flash memory sense amplifiers
Silicon Storage Technology, San Jose, CA, has been assigned a patent (8,773,934) developed by Hieu Van Tran, San Jose, CA, for a “power line compensation for flash memory sense amplifiers.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.”

The patent application was filed on Sept. 27, 2006 (11/528,748).

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