Micron Assigned Six Patents

Gettering agents in memory charge storage structures
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,748,964) developed by two co-inventors for “gettering agents in memory charge storage structures.“

The co-inventors are Rhett T. Brewer, Santa Clara, CA, and Durai V. Ramaswamy, Boise, ID.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.”

The patent application was filed on Oct. 22, 2010 (12/910,404).

Data conditioning to improve flash memory reliability
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,762,629) developed by three co-inventors for methods and apparatus “for managing storage in memory devices utilizing memory arrays of varying density memory cells.”

The co-inventors are William H. Radke, Los Gatos, CA, Vishal Sarin, Cupertino, CA, and Jung-Sheng Hoei, Newark, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus for managing storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.”

The patent application was filed on Sept. 14, 2012 (13/616,486).

Storage system, electronic system, and telecommunications system
Micron Technology, Boise, ID, has been assigned a patent (8,782,333) developed by Brian Johnson, Boise, ID, for a “storage system, electronic system, and telecommunications system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunications system are further disclosed.”

The patent application was filed on July 16, 2012 (13/550,281).

Reading and/or programming data in memory arrays
having varying available storage ranges
Micron Technology, Boise, ID, has been assigned a patent (8,780,608) developed by Kenneth J. Eldredge, Boise, ID, for “apparatuses and methods for reading and/or programming data in memory arrays having varying available storage ranges.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses and methods are disclosed, including methods for reading data from and programming data to an array of memory cells having varying available storage ranges. One such method involves determining a position of a determined value of a parameter within an available storage range of a selected memory cell of an array of memory cells.“

The patent application was filed on Jan. 23, 2012 (13/355,820).

Capacitors may include container-shaped storage node structures
Micron Technology, Boise, ID, has been assigned a patent (8,766,347) developed by three co-inventors for “capacitors may include container-shaped storage node structures.“

The co-inventors are Duane M. Goodner, Sanjeev Sapra, and Darwin Franseda Fan, Boise, ID.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged. Capacitor dielectric material and capacitor electrode material are formed along the modified storage node structure.”

The patent application was filed on Sept. 7, 2012 (13/607,230).

Spin torque transfer memory cell
Micron Technology, Boise, ID, has been assigned a patent (8,767,455) developed by two co-inventors for a “spin torque transfer memory cell structures and methods.”

The co-inventors are Stephen J. Kramer, and Gurtej S. Sandhu, Boise, ID.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.“

The patent application was filed on Jan. 22, 2013 (13/746,402).