Spansion Assigned Two Patents

Flash memory cells having trenched storage elements
Spansion, LLC, Sunnyvale, CA, has been assigned a patent (8,742,486) developed by Wei Zheng, Santa Clara, CA, Chi Chang, Saratoga, CA, and Unsoon Kim, San Jose, CA, for “flash memory cells having trenched storage elements.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.“

The patent application was filed on Feb. 5, 2007 (11/702,846).

Semiconductor memory device featuring selective data storage
in stacked memory cell structure
Spansion, Sunnyvale, CA, has been assigned a patent (8,773,885) developed by Naoharu Shinozaki, Tokyo, Japan, for a “semiconductor memory device featuring selective data storage in a stacked memory cell structure.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.“

The patent application was filed on Sept. 19, 2012 (13/622,796).