OCZ (Toshiba) Assigned Two Patents

Non-volatile solid state memory-based mass storage device
OCZ Storage Solutions, Inc., San Jose, CA, has been assigned a patent (8,724,389) developed by Ji-Hyun In, Fremont, CA, for a “non-volatile solid state memory-based mass storage device and methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits.”

The patent application was filed on July 26, 2012 (13/558,830).

Promoting endurance of non-volatile solid-state memory components
OCZ Storage Solutions, San Jose, CA, has been assigned a patent (8,738,848) developed by Franz Michael Schuette, Colorado Springs, CO, and Anthony Leach, Stockport, UK, for “methods, storage devices, and systems for promoting the endurance of non-volatile solid-state memory components.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Solid-state mass storage devices, host computer systems, and methods of managing non-volatile solid-state memory components used therein. The memory components comprise memory cells organized in functional units that are adapted to receive units of data transferred from the host computer system and correspond to the functional units of the memory component. The level of programming for each cell is reduced by performing an analysis of the bit values of the units of data to be written to at least a first of the functional units of the memory component. Depending on the analysis of 0 and 1 bit values of the units of data to be written, the bit values are inverted before writing the units of data to the first memory component.”

The patent application was filed on Dec. 27, 2011 (13/337,482).